MC908GZ60CFUE Datasheet, PDF (92/352 Pages) Freescale Semiconductor, Inc – Standard features, Features of the CPU08

Configuration Register (CONFIG)
Address: $001E
Bit 7
6
5
4
3
2
1
Bit 0
Read: 0
Write:
MCLKSEL MCLK1 MCLK0 MSCANEN TMBCLKSEL OSCENINSTOP SCIBDSRC
Reset: 0
0
0
0
See note
0
0
1
Note: MSCANEN is only reset via POR (power-on reset).
= Unimplemented
Figure 5-1. Configuration Register 2 (CONFIG2)
MCLKSEL — MCLK Source Select Bit
1 = Crystal frequency
0 = Bus frequency
MCLK1 and MCLK0 — MCLK Output Select Bits
Setting the MCLK1 and MCLK0 bits enables the PTD0/SS pin to be used as a MCLK output clock.
Once configured for MCLK, the PTD data direction register for PTD0 is used to enable and disable the
MCLK output. S e e T a b le 5 -1 fo r M C L K o p tio n s .
MCLK1
0
0
1
1
Table 5-1. MCLK Output Select
MCLK0
0
1
0
1
MCLK Frequency
MCLK not enabled
Clock
Clock divided by 2
Clock divided by 4
MSCANEN— MSCAN08 Enable Bit
Setting the MSCANEN enables the MSCAN08 module and allows the MSCAN08 to use the PTC0/PTC1
pins. See Chapter 12 MSCAN08 Controller (MSCAN08) for a more detailed description of the
MSCAN08 operation.
1 = Enables MSCAN08 module
0 = Disables the MSCAN08 module
NOTE
The MSCANEN bit is cleared by a power-on reset (POR) only. Other resets
will leave this bit unaffected.
TMBCLKSEL— Timebase Clock Select Bit
TMBCLKSEL enables an extra divide-by-128 prescaler in the timebase module. Setting this bit enables
the extra prescaler and clearing this bit disables it. See Chapter 17 Timebase Module (TBM) for a more
detailed description of the external clock operation.
1 = Enables extra divide-by-128 prescaler in timebase module
0 = Disables extra divide-by-128 prescaler in timebase module
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
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Freescale Semiconductor