MC908GZ60CFUE Datasheet, PDF (182/352 Pages) Freescale Semiconductor, Inc – Standard features, Features of the CPU08

Input/Output (I/O) Ports
When bit DDRDx is a 1, reading address $0003 reads the PTDx data latch. When bit DDRDx is a 0,
reading address $0003 reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 13-5 summarizes the operation of the port D pins.
V_DD
READ DDRD ($0007)
WRITE DDRD ($0007)
RESET
WRITE PTD ($0003)
DDRDx
PTDx
PTDPUEx
INTERNAL
PULLUP
DEVICE
PTDx
READ PTD ($0003)
Figure 13-15. Port D I/O Circuit
Table 13-5. Port D Pin Functions
PTDPUE
Bit
1
0
X
DDRD
Bit
0
0
1
PTD
Bit
X⁽¹⁾
X
X
I/O Pin
Mode
Input, V_DD(2)
Input, Hi-Z⁽⁴⁾
Output
Accesses to DDRD
Read/Write
DDRD7–DDRD0
DDRD7–DDRD0
DDRD7–DDRD0
Accesses to PTD
Read
Write
Pin
PTD7–PTD0⁽³⁾
Pin
PTD7–PTD0⁽³⁾
PTD7–PTD0
PTD7–PTD0
1. X = Don’t care
2. I/O pin pulled up to V_DD by internal pullup device.
3. Writing affects data register, but does not affect input.
4. Hi-Z = High imp[edance
13.6.3 Port D Input Pullup Enable Register
The port D input pullup enable register (PTDPUE) contains a software configurable pullup device for each
of the eight port D pins. Each bit is individually configurable and requires that the data direction register,
DDRD, bit be configured as an input. Each pullup is automatically and dynamically disabled when a port
bit’s DDRD is configured for output mode.
Address: $000F
Bit 7
6
5
4
3
2
1
Bit 0
Read:
PTDPUE7
Write:
Reset: 0
PTDPUE6
0
PTDPUE5
0
PTDPUE4
0
PTDPUE3
0
PTDPUE2
0
PTDPUE1
0
PTDPUE0
0
Figure 13-16. Port D Input Pullup Enable Register (PTDPUE)
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
182
Freescale Semiconductor