MC908GZ60CFUE Datasheet, PDF (39/352 Pages) Freescale Semiconductor, Inc – Standard features, Features of the CPU08

Input/Output (I/O) Section
Addr.
$0030
$0031
$0032
$0033
$0034
$0035
$0036
$0037
$0038
$0039
$003A
$003B
Register Name
TIM2 Channel 0 Status and ^Read:
Control Register (T2SC0) Write:
See page 293. _Reset:
TIM2 Channel 0 ^Read:
Register High (T2CH0H) Write:
See page 297. _Reset:
TIM2 Channel 0 ^Read:
Register Low (T2CH0L) Write:
See page 297. _Reset:
TIM2 Channel 1 Status and ^Read:
Control Register (T2SC1) Write:
See page 293. _Reset:
TIM2 Channel 1 ^Read:
Register High (T2CH1H) Write:
See page 297. _Reset:
TIM2 Channel 1 ^Read:
Register Low (T2CH1L) Write:
See page 297. _Reset:
PLL Control Register ^Read:
(PCTL) Write:
See page 83. _Reset:
PLL Bandwidth Control ^Read:
Register (PBWC) Write:
See page 85. _Reset:
PLL Multiplier Select High ^Read:
Register (PMSH) Write:
See page 86. _Reset:
PLL Multiplier Select Low ^Read:
Register (PMSL) Write:
See page 86. _Reset:
PLL VCO Select Range ^Read:
Register (PMRS) Write:
See page 87. _Reset:
Read:
Reserved Write:
Reset:
Bit 7
CH0F
0
0
Bit 15
Bit 7
CH1F
0
0
Bit 15
Bit 7
PLLIE
0
AUTO
0
0
0
MUL7
0
VRS7
0
0
0
6
5
4
3
2
1
CH0IE MS0B MS0A ELS0B ELS0A TOV0
0
0
0
0
0
0
14
13
12
11
10
9
Indeterminate after reset
6
5
4
3
2
1
CH1IE
Indeterminate after reset
0
MS1A ELS1B ELS1A TOV1
0
0
0
0
0
0
14
13
12
11
10
9
Indeterminate after reset
6
5
4
3
2
1
Indeterminate after reset
PLLF
PLLON
BCS
R
R
VPR1
0
1
0
0
0
0
LOCK
0
0
0
0
ACQ
0
0
0
0
0
0
0
0
0
MUL11 MUL10 MUL9
0
0
0
0
0
0
MUL6
MUL5
MUL4
MUL3
MUL2
MUL1
1
0
0
0
0
0
VRS6
VRS5
VRS4
VRS3
VRS2
VRS1
1
0
0
0
0
0
0
0
0
R
R
R
0
0
= Unimplemented
0
0
R = Reserved
0
0
U = Unaffected
Figure 2-2. Control, Status, and Data Registers (Sheet 5 of 9)
Bit 0
CH0MAX
0
Bit 8
Bit 0
CH1MAX
0
Bit 8
Bit 0
VPR0
0
R
0
MUL8
0
MUL0
0
VRS0
0
R
1
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
Freescale Semiconductor
39