MC908GZ60CFUE Datasheet, PDF (170/352 Pages) Freescale Semiconductor, Inc – Standard features, Features of the CPU08

Input/Output (I/O) Ports
Addr.
$0004
$0005
$0006
$0007
$0008
$000C
$000D
$000E
$000F
$0440
$0441
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
Data Direction Register A ^Read:
(DDRA) Write:
See page 174. _Reset:
DDRA7
0
DDRA6
0
DDRA5
0
DDRA4
0
DDRA3
0
DDRA2
0
DDRA1
0
DDRA0
0
Data Direction Register B ^Read:
(DDRB) Write:
See page 176. _Reset:
DDRB7
0
DDRB6
0
DDRB5
0
DDRB4
0
DDRB3
0
DDRB2
0
DDRB1
0
DDRB0
0
Data Direction Register C ^Read:
0
(DDRC) Write:
See page 178. _Reset:
0
DDRC6 DDRC5 DDRC4 DDRC3 DDRC2 DDRC1 DDRC0
0
0
0
0
0
0
0
Data Direction Register D ^Read:
(DDRD) Write:
See page 181. _Reset:
DDRD7
0
DDRD6
0
DDRD5
0
DDRD4
0
DDRD3
0
DDRD2
0
DDRD1
0
DDRD0
0
Port E Data Register ^Read:
0
(PTE) Write:
See page 183. _Reset:
0
PTE5
PTE4
PTE3
PTE2
PTE1
PTE0
Unaffected by reset
Data Direction Register E ^Read:
0
(DDRE) Write:
See page 184. _Reset:
0
0
DDRE5 DDRE4 DDRE3 DDRE2 DDRE1 DDRE0
0
0
0
0
0
0
0
Port A Input Pullup Enable ^Read: _PTAPUE7
Register (PTAPUE) Write:
See page 175. _Reset:
0
PTAPUE6
0
PTAPUE5
0
PTAPUE4
0
PTAPUE3
0
PTAPUE2
0
PTAPUE1
0
PTAPUE0
0
Port C Input Pullup Enable ^Read:
0
Register (PTCPUE) Write:
See page 180. _Reset:
0
PTCPUE6 PTCPUE5 PTCPUE4 PTCPUE3 PTCPUE2 PTCPUE1 PTCPUE0
0
0
0
0
0
0
0
Port D Input Pullup Enable ^Read: _PTDPUE7
Register (PTDPUE) Write:
See page 182. _Reset:
0
PTDPUE6
0
PTDPUE5
0
PTDPUE4
0
PTDPUE3
0
PTDPUE2
0
PTDPUE1
0
PTDPUE0
0
Port F Data Register Read:
(PTF)
See page 185.
Write:
Reset:
PTF7
PTF6
PTF5
PTF4 PTAF3
Unaffected by reset
PTF2
PTF1
PTF0
Port G Data Register Read:
(PTG)
See page 186.
Write:
Reset:
PTG7
PTG6
PTG5
PTG4
PTG3
Unaffected by reset
PTG2
PTG1
PTG0
= Unimplemented
Figure 13-1. I/O Port Register Summary (Sheet 2 of 3)
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
170
Freescale Semiconductor