MC908GZ60CFUE Datasheet, PDF (114/352 Pages) Freescale Semiconductor, Inc – Standard features, Features of the CPU08

External Interrupt (IRQ)
8.6 IRQ Status and Control Register
The IRQ status and control register (INTSCR) controls and monitors operation of the IRQ module. The
INTSCR:
• Shows the state of the IRQ flag
• Clears the IRQ latch
• Masks IRQ interrupt request
• Controls triggering sensitivity of the IRQ interrupt pin
Address:
Read:
Write:
Reset:
$001D
Bit 7
6
5
4
3
2
1
0
0
0
0
IRQF
0
IMASK
ACK
0
0
0
0
0
0
0
= Unimplemented
Figure 8-3. IRQ Status and Control Register (INTSCR)
Bit 0
MODE
0
IRQF — IRQ Flag Bit
This read-only status bit is high when the IRQ interrupt is pending.
1 = IRQ interrupt pending
0 = IRQ interrupt not pending
ACK — IRQ Interrupt Request Acknowledge Bit
Writing a 1 to this write-only bit clears the IRQ latch. ACK always reads as 0. Reset clears ACK.
IMASK — IRQ Interrupt Mask Bit
Writing a 1 to this read/write bit disables IRQ interrupt requests. Reset clears IMASK.
1 = IRQ interrupt requests disabled
0 = IRQ interrupt requests enabled
MODE — IRQ Edge/Level Select Bit
This read/write bit controls the triggering sensitivity of the IRQ pin. Reset clears MODE.
1 = IRQ interrupt requests on falling edges and low levels
0 = IRQ interrupt requests on falling edges only
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
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Freescale Semiconductor