MC908GZ60CFUE Datasheet, PDF (289/352 Pages) Freescale Semiconductor, Inc – Standard features, Features of the CPU08

Interrupts
Setting MS0B links channels 0 and 1 and configures them for buffered PWM operation. The TIM2
channel 0 registers (T2CH0H:T2CH0L) initially control the buffered PWM output. TIM2 status control
register 0 (T2SC0) controls and monitors the PWM signal from the linked channels. MS0B takes priority
over MS0A.
Setting MS2B links channels 2 and 3 and configures them for buffered PWM operation. The TIM2
channel 2 registers (T2CH2H:T2CH2L) initially control the buffered PWM output. TIM2 status control
register 2 (T2SC2) controls and monitors the PWM signal from the linked channels. MS2B takes priority
over MS2A.
Setting MS4B links channels 4 and 5 and configures them for buffered PWM operation. The TIM2
channel 4 registers (T2CH4H:T2CH4L) initially control the buffered PWM output. TIM2 status control
register 4 (T2SC4) controls and monitors the PWM signal from the linked channels. MS4B takes priority
over MS4A.
Clearing the toggle-on-overflow bit, TOVx, inhibits output toggles on TIM2 overflows. Subsequent output
compares try to force the output to a state it is already in and have no effect. The result is a 0% duty cycle
output.
Setting the channel x maximum duty cycle bit (CHxMAX) and setting the TOVx bit generates a 100% duty
cycle output. (See 19.8.4 TIM2 Channel Status and Control Registers.)
19.4 Interrupts
The following TIM2 sources can generate interrupt requests:
• TIM2 overflow flag (TOF) — The TOF bit is set when the TIM2 counter reaches the modulo value
programmed in the TIM2 counter modulo registers. The TIM2 overflow interrupt enable bit, TOIE,
enables TIM2 overflow interrupt requests. TOF and TOIE are in the TIM2 status and control
register.
• TIM2 channel flags (CH5F:CH0F) — The CHxF bit is set when an input capture or output compare
occurs on channel x. Channel x TIM2 CPU interrupt requests are controlled by the channel x
interrupt enable bit, CHxIE.
19.5 Low-Power Modes
The WAIT and STOP instructions put the MCU in low-power standby modes.
19.5.1 Wait Mode
The TIM2 remains active after the execution of a WAIT instruction. In wait mode, the TIM2 registers are
not accessible by the CPU. Any enabled CPU interrupt request from the TIM2 can bring the MCU out of
wait mode.
If TIM2 functions are not required during wait mode, reduce power consumption by stopping the TIM2
before executing the WAIT instruction.
19.5.2 Stop Mode
The TIM2 is inactive after the execution of a STOP instruction. The STOP instruction does not affect
register conditions or the state of the TIM2 counter. TIM2 operation resumes when the MCU exits stop
mode.
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
Freescale Semiconductor
289