MC908GZ60CFUE Datasheet, PDF (149/352 Pages) Freescale Semiconductor, Inc – Standard features, Features of the CPU08

Clock System
The above parameters can be set by programming the bus timing registers, CBTR0 and CBTR1. See
12.13.3 MSCAN08 Bus Timing Register 0 and 12.13.4 MSCAN08 Bus Timing Register 1.
NOTE
It is the user’s responsibility to make sure that the bit timing settings are in
compliance with the CAN standard,
Table 12-8 gives an overview on the CAN conforming segment settings and the related parameter values.
NRZ SIGNAL
SYNC
_SEG
TIME SEGMENT 1
(PROP_SEG + PHASE_SEG1)
TIME SEG. 2
(PHASE_SEG2)
1
4 ... 16
2 ... 8
8... 25 TIME QUANTA
= 1 BIT TIME
SAMPLE POINT
(SINGLE OR TRIPLE SAMPLING)
Figure 12-9. Segments Within the Bit Time
.
Table 12-3. Time Segment Syntax
SYNC_SEG
Transmit point
Sample point
System expects transitions to occur on the bus during this
period.
A node in transmit mode will transfer a new value to the CAN
bus at this point.
A node in receive mode will sample the bus at this point. If the
three samples per bit option is selected then this point marks
the position of the third sample.
Table 12-4. CAN Standard Compliant Bit Time Segment Settings
Time
Segment 1
5 .. 10
4 .. 11
5 .. 12
6 .. 13
7 .. 14
8 .. 15
9 .. 16
TSEG1
4 .. 9
3 .. 10
4 .. 11
5 .. 12
6 .. 13
7 .. 14
8 .. 15
Time
Segment 2
2
3
4
5
6
7
8
TSEG2
1
2
3
4
5
6
7
Synchronized
Jump Width
1 .. 2
1 .. 3
1 .. 4
1 .. 4
1 .. 4
1 .. 4
1 .. 4
SJW
0 .. 1
0 .. 2
0 .. 3
0 .. 3
0 .. 3
0 .. 3
0 .. 3
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
Freescale Semiconductor
149