MC908GZ60CFUE Datasheet, PDF (293/352 Pages) Freescale Semiconductor, Inc – Standard features, Features of the CPU08

I/O Registers
19.8.3 TIM2 Counter Modulo Registers
The read/write TIM2 modulo registers contain the modulo value for the TIM2 counter. When the TIM2
counter reaches the modulo value, the overflow flag (TOF) becomes set, and the TIM2 counter resumes
counting from $0000 at the next timer clock. Writing to the high byte (T2MODH) inhibits the TOF bit and
overflow interrupts until the low byte (T2MODL) is written. Reset sets the TIM2 counter modulo registers.
Address: $002E T2MODH
Bit 7
6
5
4
3
2
1
Bit 0
Read:
BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10
BIT 9
BIT 8
Write:
Reset: 1
1
1
1
1
1
1
1
Address: $002F T2MODL
Bit 7
6
5
4
3
2
1
Bit 0
Read:
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Write:
Reset: 1
1
1
1
1
1
1
1
Figure 19-7. TIM2 Counter Modulo Registers (T2MODH and T2MODL)
NOTE
Reset the TIM2 counter before writing to the TIM2 counter modulo registers.
19.8.4 TIM2 Channel Status and Control Registers
Each of the TIM2 channel status and control registers:
• Flags input captures and output compares
• Enables input capture and output compare interrupts
• Selects input capture, output compare, or PWM operation
• Selects high, low, or toggling output on output compare
• Selects rising edge, falling edge, or any edge as the active input capture trigger
• Selects output toggling on TIM2 overflow
• Selects 0% and 100% PWM duty cycle
• Selects buffered or unbuffered output compare/PWM operation
Address: $0030
Bit 7
Read: CH0F
Write: 0
Reset: 0
T2SC0
6
5
CH0IE MS0B
0
0
= Unimplemented
4
MS0A
0
3
2
ELS0B ELS0A
0
0
1
TOV0
0
Figure 19-8. TIM2 Channel Status and Control Registers
(T2SC0:T2SC5)
Bit 0
CH0MAX
0
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
Freescale Semiconductor
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