MC908GZ60CFUE Datasheet, PDF (183/352 Pages) Freescale Semiconductor, Inc – Standard features, Features of the CPU08

Port E
PTDPUE7–PTDPUE0 — Port D Input Pullup Enable Bits
These writable bits are software programmable to enable pullup devices on an input port bit.
1 = Corresponding port D pin configured to have internal pullup
0 = Corresponding port D pin has internal pullup disconnected
13.7 Port E
Port E is a 6-bit special-function port that shares two of its pins with the enhanced serial communications
interface (ESCI) module.
13.7.1 Port E Data Register
The port E data register contains a data latch for each of the six port E pins.
Address: $0008
Bit 7
6
5
4
3
2
1
Bit 0
Read: 0
Write:
0
PTE5
PTE4
PTE3
PTE2
PTE1
PTE0
Reset:
Unaffected by reset
Alternate Function:
RxD
TxD
= Unimplemented
Figure 13-17. Port E Data Register (PTE)
PTE5–PTE0 — Port E Data Bits
These read/write bits are software-programmable. Data direction of each port E pin is under the control
of the corresponding bit in data direction register E. Reset has no effect on port E data.
NOTE
Data direction register E (DDRE) does not affect the data direction of port
E pins that are being used by the ESCI module. However, the DDRE bits
always determine whether reading port E returns the states of the latches
or the states of the pins. See Table 13-6.
RxD — SCI Receive Data Input
The PTE1/RxD pin is the receive data input for the ESCI module.
When the enable SCI bit, ENSCI, is clear, the ESCI module is disabled, and the PTE1/RxD pin is
available for general-purpose I/O. See Chapter 14 Enhanced Serial Communications Interface (ESCI)
Module.
TxD — SCI Transmit Data Output
The PTE0/TxD pin is the transmit data output for the ESCI module. When the enable SCI bit, ENSCI,
is clear, the ESCI module is disabled, and the PTE0/TxD pin is available for general-purpose I/O. See
Chapter 14 Enhanced Serial Communications Interface (ESCI) Module.
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
Freescale Semiconductor
183