MC908GZ60CFUE Datasheet, PDF (282/352 Pages) Freescale Semiconductor, Inc – Standard features, Features of the CPU08

Timer Interface Module (TIM2)
Addr.
$002B
$002C
$002D
$002E
$002F
$0030
$0031
$0032
$0033
$0034
$0035
$0456
Register Name
TIM2 Status and Control ^Read:
Register (T2SC) Write:
See page 291. _Reset:
TIM2 Counter Register High ^Read:
(T2CNTH) Write:
See page 292. _Reset:
TIM2 Counter Register Low ^Read:
(T2CNTL) Write:
See page 292. _Reset:
TIM2 Modulo Register High ^Read:
(T2MODH) Write:
See page 293. _Reset:
TIM2 Modulo Register Low ^Read:
(T2MODL) Write:
See page 293. _Reset:
TIM2 Channel 0 Status and ^Read:
Control Register (T2SC0) Write:
See page 293. _Reset:
TIM2 Channel 0 Register High ^Read:
(T2CH0H) Write:
See page 297. _Reset:
TIM2 Channel 0 Register Low ^Read:
(T2CH0L) Write:
See page 297. _Reset:
TIM2 Channel 1 Status and ^Read:
Control Register (T2SC1) Write:
See page 293. _Reset:
TIM2 Channel 1 Register High ^Read:
(T2CH1H) Write:
See page 297. _Reset:
TIM2 Channel 1 Register Low ^Read:
(T2CH1L) Write:
See page 297. _Reset:
TIM2 Channel 2 Status and ^Read:
Control Register (T2SC2) Write:
See page 293. _Reset:
Bit 7
TOF
0
0
Bit 15
0
Bit 7
0
Bit 15
1
Bit 7
1
CH0F
0
0
Bit 15
Bit 7
CH1F
0
0
Bit 15
Bit 7
CH2F
0
0
6
5
4
3
2
0
0
TOIE TSTOP
PS2
TRST
0
1
0
0
0
14
13
12
11
10
0
0
0
0
0
6
5
4
3
2
0
0
0
0
0
14
13
12
11
10
1
1
1
1
1
6
5
4
3
2
1
1
1
1
1
CH0IE MS0B MS0A ELS0B ELS0A
0
0
0
0
0
14
13
12
11
10
Indeterminate after reset
6
5
4
3
2
CH1IE
Indeterminate after reset
0
MS1A ELS1B ELS1A
0
0
0
0
0
14
13
12
11
10
Indeterminate after reset
6
5
4
3
2
Indeterminate after reset
CH2IE MS2B MS2A ELS2B ELS2A
0
0
0
0
0
= Unimplemented
Figure 19-3. TIM2 I/O Register Summary (Sheet 1 of 2)
1
Bit 0
PS1
PS0
0
0
9
Bit 8
0
0
1
Bit 0
0
0
9
Bit 8
1
1
1
Bit 0
1
1
TOV0 CH0MAX
0
0
9
Bit 8
1
Bit 0
TOV1 CH1MAX
0
0
9
Bit 8
1
Bit 0
TOV2 CH2MAX
0
0
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
282
Freescale Semiconductor