S912XEP100J5MAG Datasheet, PDF (91/1324 Pages) Freescale Semiconductor, Inc – Features of the MC9S12XE-Family are listed here. Please see Table D-2.for memory options and Table D-2. for the peripheral features that are available on the different family members.

Chapter 2 Port Integration Module (S12XEPIMV1)
Table 2-2 shows all the pins and their functions that are controlled by the Port Integration Module. Refer
to the SOC Guide for the availability of the individual pins in the different package options.
NOTE
If there is more than one function associated with a pin, the priority is
indicated by the position in the table from top (highest priority) to bottom
(lowest priority).
Table 2-2. Pin Functions and Priorities
Port Pin Name
-
BKGD
A PA[7:0]
B PB[7:1]
PB[0]
C PC[7:0]
D PD[7:0]
Pin Function
& Priority⁽¹⁾
MODC ⁽²⁾
BKGD
ADDR[15:8]
mux
IVD[15:8] ⁽³⁾
GPIO
ADDR[7:1]
mux
IVD[7:1] ³
GPIO
ADDR[0]
mux
IVD0 ³
UDS
GPIO
DATA[15:8]
GPIO
DATA[7:0]
GPIO
I/O
Description
I MODC input during RESET
I/O S12X_BDM communication pin
O High-order external bus address output
(multiplexed with IVIS data)
I/O General-purpose I/O
O Low-order external bus address output
(multiplexed with IVIS data)
I/O General-purpose I/O
O Low-order external bus address output
(multiplexed with IVIS data)
O Upper data strobe
I/O General-purpose I/O
I/O High-order bidirectional data input/output
Configurable for reduced input threshold
I/O General-purpose I/O
I/O Low-order bidirectional data input/output
Configurable for reduced input threshold
I/O General-purpose I/O
Pin Function
after Reset
BKGD
Mode
dependent ⁽⁴⁾
Mode
dependent ⁴
Mode
dependent ⁴
Mode
dependent ⁴
MC9S12XE-Family Reference Manual Rev. 1.25
Freescale Semiconductor
91