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S912XEP100J5MAG Datasheet, PDF (275/1324 Pages) Freescale Semiconductor, Inc – Features of the MC9S12XE-Family are listed here. Please see Table D-2.for memory options and Table D-2. for the peripheral features that are available on the different family members. | |||
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6.5 Initialization/Application Information
Chapter 6 Interrupt (S12XINTV2)
6.5.1 Initialization
After system reset, software should:
⢠Initialize the interrupt vector base register if the interrupt vector table is not located at the default
location (0xFF10â0xFFF9).
⢠Initialize the interrupt processing level conï¬guration data registers (INT_CFADDR,
INT_CFDATA0â7) for all interrupt vector requests with the desired priority levels and the request
target (CPU or XGATE module). It might be a good idea to disable unused interrupt requests.
⢠If the XGATE module is used, setup the XGATE interrupt priority register (INT_XGPRIO) and
conï¬gure the XGATE module (please refer the XGATE Block Guide for details).
⢠Enable I maskable interrupts by clearing the I bit in the CCR.
⢠Enable the X maskable interrupt by clearing the X bit in the CCR (if required).
6.5.2 Interrupt Nesting
The interrupt request priority level scheme makes it possible to implement priority based interrupt request
nesting for the I bit maskable interrupt requests handled by the CPU.
⢠I bit maskable interrupt requests can be interrupted by an interrupt request with a higher priority,
so that there can be up to seven nested I bit maskable interrupt requests at a time (refer to Figure 6-
14 for an example using up to three nested interrupt requests).
I bit maskable interrupt requests cannot be interrupted by other I bit maskable interrupt requests per
default. In order to make an interrupt service routine (ISR) interruptible, the ISR must explicitly clear the
I bit in the CCR (CLI). After clearing the I bit, I bit maskable interrupt requests with higher priority can
interrupt the current ISR.
An ISR of an interruptible I bit maskable interrupt request could basically look like this:
⢠Service interrupt, e.g., clear interrupt ï¬ags, copy data, etc.
⢠Clear I bit in the CCR by executing the instruction CLI (thus allowing interrupt requests with
higher priority)
⢠Process data
⢠Return from interrupt by executing the instruction RTI
MC9S12XE-Family Reference Manual Rev. 1.25
Freescale Semiconductor
275
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