S912XEP100J5MAG Datasheet, PDF(816/1324 Page) Freescale Semiconductor, Inc – Features of the MC9S12XE-Family are listed here. Please see Table D-2.for memory options and Table D-2. for the peripheral features that are available on the different family members.

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S912XEP100J5MAG Datasheet, PDF (816/1324 Pages) Freescale Semiconductor, Inc – Features of the MC9S12XE-Family are listed here. Please see Table D-2.for memory options and Table D-2. for the peripheral features that are available on the different family members.

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Chapter 23 Voltage Regulator (S12VREGL3V3V1)

3. Shutdown mode

Controlled by VREGEN (see device level speciï¬cation for connectivity of VREGEN).

This mode is characterized by minimum power consumption. The regulator outputs are in a high-

impedance state, only the POR feature is available, LVD, LVR and HTD are disabled. The API

internal RC oscillator clock is not available.

This mode must be used to disable the chip internal regulator VREG_3V3, i.e., to bypass the

VREG_3V3 to use external supplies.

23.1.3 Block Diagram

Figure 23-1 shows the function principle of VREG_3V3 by means of a block diagram. The regulator core

REG consists of three parallel subblocks, REG1, REG2 and REG3, providing three independent output

voltages.

MC9S12XE-Family Reference Manual Rev. 1.25

816

Freescale Semiconductor

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