S912XEP100J5MAG Datasheet, PDF(133/1324 Page) Freescale Semiconductor, Inc – Features of the MC9S12XE-Family are listed here. Please see Table D-2.for memory options and Table D-2. for the peripheral features that are available on the different family members.

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S912XEP100J5MAG Datasheet, PDF (133/1324 Pages) Freescale Semiconductor, Inc – Features of the MC9S12XE-Family are listed here. Please see Table D-2.for memory options and Table D-2. for the peripheral features that are available on the different family members.

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Chapter 2 Port Integration Module (S12XEPIMV1)

Table 2-35. DDRM Register Field Descriptions (continued)

Field

4

DDRM

3

DDRM

2

DDRM

1

DDRM

0

DDRM

Description

Port M data directionâ

This register controls the data direction of pin 4.

The enabled CAN2, routed CAN0, or routed CAN4 forces the I/O state to be an input. Depending on the conï¬guration

of the enabled routed SPI0 this pin will be forced to be input or output.In those cases the data direction bits will not

change. The DDRM bits revert to controlling the I/O direction of a pin when the associated peripheral module is

disabled.

1 Associated pin is conï¬gured as output.

0 Associated pin is conï¬gured as input.

Port M data directionâ

This register controls the data direction of pin 3.

The enabled CAN1 or routed CAN0 forces the I/O state to be an output. Depending on the conï¬guration of the

enabled routed SPI0 this pin will be forced to be input or output. In those cases the data direction bits will not change.

The DDRM bits revert to controlling the I/O direction of a pin when the associated peripheral module is disabled.

1 Associated pin is conï¬gured as output.

0 Associated pin is conï¬gured as input.

Port M data directionâ

This register controls the data direction of pin 2.

The enabled CAN1 or routed CAN0 forces the I/O state to be an input. Depending on the conï¬guration of the enabled

routed SPI0 this pin will be forced to be input or output.In those cases the data direction bits will not change. The

DDRM bits revert to controlling the I/O direction of a pin when the associated peripheral module is disabled.

1 Associated pin is conï¬gured as output.

0 Associated pin is conï¬gured as input.

Port M data directionâ

This register controls the data direction of pin 1.

The enabled CAN0 forces the I/O state to be an output. In those cases the data direction bits will not change. The

DDRM bits revert to controlling the I/O direction of a pin when the associated peripheral module is disabled.

1 Associated pin is conï¬gured as output.

0 Associated pin is conï¬gured as input.

Port M data directionâ

This register controls the data direction of pin 0.

The enabled CAN0 forces the I/O state to be an input. In those cases the data direction bits will not change. The

DDRM bits revert to controlling the I/O direction of a pin when the associated peripheral module is disabled.

1 Associated pin is conï¬gured as output.

0 Associated pin is conï¬gured as input.

NOTE

Due to internal synchronization circuits, it can take up to 2 bus clock cycles

until the correct value is read on PTM or PTIM registers, when changing the

DDRM register.

MC9S12XE-Family Reference Manual Rev. 1.25

Freescale Semiconductor

133

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