S912XEP100J5MAG Datasheet, PDF (140/1324 Pages) Freescale Semiconductor, Inc – Features of the MC9S12XE-Family are listed here. Please see Table D-2.for memory options and Table D-2. for the peripheral features that are available on the different family members.

Chapter 2 Port Integration Module (S12XEPIMV1)
2.3.48 Port P Reduced Drive Register (RDRP)
Address 0x025B
R
W
Reset
7
RDRP7
0
1. Read: Anytime.
Write: Anytime.
6
RDRP6
5
RDRP5
4
RDRP4
3
RDRP3
2
RDRP2
0
0
0
0
0
Figure 2-46. Port P Reduced Drive Register (RDRP)
Access: User read/write⁽¹⁾
1
0
RDRP1
RDRP0
0
0
Table 2-44. RDRP Register Field Descriptions
Field
7-0
RDRP
Description
Port P reduced drive—Select reduced drive for outputs
This register configures the drive strength of output pins 7 through 0 as either full or reduced independent of the
function used on the pins. If a pin is used as input this bit has no effect.
1 Reduced drive selected (approx. 1/5 of the full drive strength).
0 Full drive strength enabled.
2.3.49 Port P Pull Device Enable Register (PERP)
Address 0x025C
R
W
Reset
7
PPSP7
0
1. Read: Anytime.
Write: Anytime.
6
PPSP6
5
PPSP5
4
PPSP4
3
PPSP3
2
PPSP2
Access: User read/write⁽¹⁾
1
0
PPSP1
PPSP0
0
0
0
0
0
0
0
Figure 2-47. Port P Pull Device Enable Register (PERP)
Table 2-45. PERP Register Field Descriptions
Field
7-0
PERP
Description
Port P pull device enable—Enable pull devices on input pins
These bits configure whether a pull device is activated, if the associated pin is used as an input. This bit has no effect
if the pin is used as an output. Out of reset no pull device is enabled.
1 Pull device enabled.
0 Pull device disabled.
MC9S12XE-Family Reference Manual Rev. 1.25
140
Freescale Semiconductor