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S912XEP100J5MAG Datasheet, PDF (907/1324 Pages) Freescale Semiconductor, Inc – Features of the MC9S12XE-Family are listed here. Please see Table D-2.for memory options and Table D-2. for the peripheral features that are available on the different family members. | |||
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Chapter 25 256 KByte Flash Module (S12XFTM256K2V1)
Table 25-14. FECCRIX Field Descriptions
Field
Description
2-0
ECC Error Register Indexâ The ECCRIX bits are used to select which word of the FECCR register array is
ECCRIX[2:0] being read. See Section 25.3.2.13, âFlash ECC Error Results Register (FECCR),â for more details.
25.3.2.5 Flash Conï¬guration Register (FCNFG)
The FCNFG register enables the Flash command complete interrupt and forces ECC faults on Flash array
read access from the CPU or XGATE.
Offset Module Base + 0x0004
R
W
Reset
7
CCIE
0
6
5
4
3
2
0
0
0
0
IGNSF
0
0
0
0
0
= Unimplemented or Reserved
Figure 25-9. Flash Conï¬guration Register (FCNFG)
1
FDFD
0
0
FSFD
0
CCIE, IGNSF, FDFD, and FSFD bits are readable and writable while remaining bits read 0 and are not
writable.
Table 25-15. FCNFG Field Descriptions
Field
7
CCIE
4
IGNSF
Description
Command Complete Interrupt Enable â The CCIE bit controls interrupt generation when a Flash command
has completed.
0 Command complete interrupt disabled
1 An interrupt will be requested whenever the CCIF ï¬ag in the FSTAT register is set (see Section 25.3.2.7)
Ignore Single Bit Fault â The IGNSF controls single bit fault reporting in the FERSTAT register (see
Section 25.3.2.8).
0 All single bit faults detected during array reads are reported
1 Single bit faults detected during array reads are not reported and the single bit fault interrupt will not be
generated
MC9S12XE-Family Reference Manual Rev. 1.25
Freescale Semiconductor
907
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