S912XEP100J5MAG Datasheet, PDF (471/1324 Pages) Freescale Semiconductor, Inc – Features of the MC9S12XE-Family are listed here. Please see Table D-2.for memory options and Table D-2. for the peripheral features that are available on the different family members.

Chapter 11 S12XE Clocks and Reset Generator (S12XECRGV1)
S12X_MMC
Voltage
Regulator
Illegal Address Reset
Power on Reset
Low Voltage Reset
RESET
XCLKS
Clock
Monitor
EXTAL
XTAL
Oscillator
ICRG
CM Fail
OSCCLK
Reset
Generator
Clock Quality
Checker
COP
RTI
V_DDPLL
V_SSPLL
PLLCLK
IPLL
Registers
Clock and Reset Control
Figure 11-1. Block diagram of S12XECRG
11.2 Signal Description
This section lists and describes the signals that connect off chip.
System Reset
Bus Clock
Core Clock
Oscillator Clock
Real Time Interrupt
PLL Lock Interrupt
Self Clock Mode
Interrupt
11.2.1 V_DDPLL, V_SSPLL
These pins provides operating voltage (V_DDPLL) and ground (V_SSPLL) for the IPLL circuitry. This allows
the supply voltage to the IPLL to be independently bypassed. Even if IPLL usage is not required V_DDPLL
and V_SSPLL must be connected to properly.
11.2.2 RESET
RESET is an active low bidirectional reset pin. As an input it initializes the MCU asynchronously to a
known start-up state. As an open-drain output it indicates that an system reset (internal to MCU) has been
triggered.
MC9S12XE-Family Reference Manual Rev. 1.25
Freescale Semiconductor
471