S912XEP100J5MAG Datasheet, PDF (235/1324 Pages) Freescale Semiconductor, Inc – Features of the MC9S12XE-Family are listed here. Please see Table D-2.for memory options and Table D-2. for the peripheral features that are available on the different family members.

Chapter 4 Memory Protection Unit (S12XMPUV1)
Table 4-9. MPUDESC1 Field Descriptions
Field
Description
7–0
Memory range lower boundary address bits — The LOW_ADDR[18:11] bits represent bits [18:11] of the
LOW_ADDR[ global memory address that is used as the lower boundary for the described memory range.
18:11]
4.3.1.8 MPU Descriptor Register 2 (MPUDESC2)
Address: Module Base + 0x0008
7
6
5
4
3
2
1
0
R
LOW_ADDR[10:3]
W
Reset
0
0
0
0
0
0
0
0
Figure 4-10. MPU Descriptor Register 2 (MPUDESC2)
Read: Anytime
Write: Anytime
Table 4-10. MPUDESC2 Field Descriptions
Field
Description
7–0
Memory range lower boundary address bits — The LOW_ADDR[10:3] bits represent bits [10:3] of the global
LOW_ADDR[ memory address that is used as the lower boundary for the described memory range.
10:3]
4.3.1.9 MPU Descriptor Register 3 (MPUDESC3)
Address: Module Base + 0x0009
7
6
5
4
3
2
1
0
R
0
0
WP
NEX
W
HIGH_ADDR[22:19]
Reset
0
0
0
0
1
1
1
1
Figure 4-11. MPU Descriptor Register 3 (MPUDESC3)
Read: Anytime
Write: Anytime
Table 4-11. MPUDESC3 Field Descriptions
Field
7
WP
Description
Write-Protect bit — The WP bit causes the described memory range to be treated as write-protected. If this
bit is set every attempt to write in the described memory range causes an access violation.
MC9S12XE-Family Reference Manual Rev. 1.25
Freescale Semiconductor
235