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S912XEP100J5MAG Datasheet, PDF (612/1324 Pages) Freescale Semiconductor, Inc – Features of the MC9S12XE-Family are listed here. Please see Table D-2.for memory options and Table D-2. for the peripheral features that are available on the different family members. | |||
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Chapter 16 Freescaleâs Scalable Controller Area Network (S12MSCANV3)
1. Read: Anytime
Write: Anytime when out of initialization mode; exceptions are read-only RXACT and SYNCH, RXFRM (which is set by the
module only), and INITRQ (which is also writable in initialization mode)
NOTE
The CANCTL0 register, except WUPE, INITRQ, and SLPRQ, is held in the
reset state when the initialization mode is active (INITRQ = 1 and
INITAK = 1). This register is writable again as soon as the initialization
mode is exited (INITRQ = 0 and INITAK = 0).
Table 16-3. CANCTL0 Register Field Descriptions
Field
Description
7
RXFRM
6
RXACT
5
CSWAI(2)
4
SYNCH
3
TIME
2
WUPE(3)
Received Frame Flag â This bit is read and clear only. It is set when a receiver has received a valid message
correctly, independently of the ï¬lter conï¬guration. After it is set, it remains set until cleared by software or reset.
Clearing is done by writing a 1. Writing a 0 is ignored. This bit is not valid in loopback mode.
0 No valid message was received since last clearing this ï¬ag
1 A valid message was received since last clearing of this ï¬ag
Receiver Active Status â This read-only ï¬ag indicates the MSCAN is receiving a message(1). The ï¬ag is
controlled by the receiver front end. This bit is not valid in loopback mode.
0 MSCAN is transmitting or idle
1 MSCAN is receiving a message (including when arbitration is lost)
CAN Stops in Wait Mode â Enabling this bit allows for lower power consumption in wait mode by disabling all
the clocks at the CPU bus interface to the MSCAN module.
0 The module is not affected during wait mode
1 The module ceases to be clocked during wait mode
Synchronized Status â This read-only ï¬ag indicates whether the MSCAN is synchronized to the CAN bus and
able to participate in the communication process. It is set and cleared by the MSCAN.
0 MSCAN is not synchronized to the CAN bus
1 MSCAN is synchronized to the CAN bus
Timer Enable â This bit activates an internal 16-bit wide free running timer which is clocked by the bit clock rate.
If the timer is enabled, a 16-bit time stamp will be assigned to each transmitted/received message within the
active TX/RX buffer. Right after the EOF of a valid message on the CAN bus, the time stamp is written to the
highest bytes (0x000E, 0x000F) in the appropriate buffer (see Section 16.3.3, âProgrammerâs Model of Message
Storageâ). In loopback mode no receive timestamp is generated. The internal timer is reset (all bits set to 0) when
disabled. This bit is held low in initialization mode.
0 Disable internal MSCAN timer
1 Enable internal MSCAN timer
Wake-Up Enable â This conï¬guration bit allows the MSCAN to restart from sleep mode or from power down
mode (entered from sleep) when trafï¬c on CAN is detected (see Section 16.4.5.5, âMSCAN Sleep Modeâ). This
bit must be conï¬gured before sleep mode entry for the selected function to take effect.
0 Wake-up disabled â The MSCAN ignores trafï¬c on CAN
1 Wake-up enabled â The MSCAN is able to restart
MC9S12XE-Family Reference Manual Rev. 1.25
612
Freescale Semiconductor
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