S912XEP100J5MAG Datasheet, PDF (700/1324 Pages) Freescale Semiconductor, Inc – Features of the MC9S12XE-Family are listed here. Please see Table D-2.for memory options and Table D-2. for the peripheral features that are available on the different family members.

Chapter 19 Pulse-Width Modulator (S12PWM8B8CV1)
Module Base + 0x0003
7
6
5
4
3
2
1
R
0
0
PCKB2
PCKB1
PCKB0
PCKA2
PCKA1
W
Reset
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 19-6. PWM Prescale Clock Select Register (PWMPRCLK)
Read: Anytime
Write: Anytime
NOTE
PCKB2–0 and PCKA2–0 register bits can be written anytime. If the clock
pre-scale is changed while a PWM signal is being generated, a truncated or
stretched pulse can occur during the transition.
Table 19-5. PWMPRCLK Field Descriptions
0
PCKA0
0
Field
Description
6–4
PCKB[2:0]
2–0
PCKA[2:0]
Prescaler Select for Clock B — Clock B is one of two clock sources which can be used for channels 2, 3, 6, or
7. These three bits determine the rate of clock B, as shown in Table 19-6.
Prescaler Select for Clock A — Clock A is one of two clock sources which can be used for channels 0, 1, 4 or
5. These three bits determine the rate of clock A, as shown in Table 19-7.
s
Table 19-6. Clock B Prescaler Selects
PCKB2
0
0
0
0
1
1
1
1
PCKB1
0
0
1
1
0
0
1
1
PCKB0
0
1
0
1
0
1
0
1
Value of Clock B
Bus clock
Bus clock / 2
Bus clock / 4
Bus clock / 8
Bus clock / 16
Bus clock / 32
Bus clock / 64
Bus clock / 128
Table 19-7. Clock A Prescaler Selects
PCKA2
0
0
0
0
1
1
1
1
PCKA1
0
0
1
1
0
0
1
1
PCKA0
0
1
0
1
0
1
0
1
Value of Clock A
Bus clock
Bus clock / 2
Bus clock / 4
Bus clock / 8
Bus clock / 16
Bus clock / 32
Bus clock / 64
Bus clock / 128
MC9S12XE-Family Reference Manual Rev. 1.25
700
Freescale Semiconductor