S912XEP100J5MAG Datasheet, PDF (107/1324 Pages) Freescale Semiconductor, Inc – Features of the MC9S12XE-Family are listed here. Please see Table D-2.for memory options and Table D-2. for the peripheral features that are available on the different family members.

Chapter 2 Port Integration Module (S12XEPIMV1)
Table 2-3. Pin Configuration Summary
DDR
IO
RDR
PE
PS⁽¹⁾
IE⁽²⁾
Function
0
x
x
0
x
0
0
x
x
1
0
0
0
x
x
1
1
0
0
x
x
0
0
1
0
x
x
0
1
1
0
x
x
1
0
1
0
x
x
1
1
1
1
0
0
x
x
0
1
1
0
x
x
0
1
0
1
x
x
0
1
1
1
x
x
0
1
0
0
x
0
1
1
1
0
x
1
1
1
0
1
x
0
1
1
1
1
x
1
1
1. Always “0” on Port A, B, C, D, E, K, AD0, and AD1.
2. Applicable only on Port P, H, and J.
Input
Input
Input
Input
Input
Input
Input
Output, full drive to 0
Output, full drive to 1
Output, reduced drive to 0
Output, reduced drive to 1
Output, full drive to 0
Output, full drive to 1
Output, reduced drive to 0
Output, reduced drive to 1
Pull Device
Disabled
Pull Up
Pull Down
Disabled
Disabled
Pull Up
Pull Down
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Interrupt
Disabled
Disabled
Disabled
Falling edge
Rising edge
Falling edge
Rising edge
Disabled
Disabled
Disabled
Disabled
Falling edge
Rising edge
Falling edge
Rising edge
NOTE
All register bits in this module are completely synchronous to internal
clocks during a register read.
MC9S12XE-Family Reference Manual Rev. 1.25
Freescale Semiconductor
107