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S912XEP100J5MAG Datasheet, PDF (268/1324 Pages) Freescale Semiconductor, Inc – Features of the MC9S12XE-Family are listed here. Please see Table D-2.for memory options and Table D-2. for the peripheral features that are available on the different family members. | |||
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Chapter 6 Interrupt (S12XINTV2)
6.3.2.3
Priority
low
high
Table 6-6. XGATE Interrupt Priority Levels
XILVL2
0
0
0
0
1
1
1
1
XILVL1
0
0
1
1
0
0
1
1
XILVL0
0
1
0
1
0
1
0
1
Meaning
Interrupt request is disabled
Priority level 1
Priority level 2
Priority level 3
Priority level 4
Priority level 5
Priority level 6
Priority level 7
Interrupt Request Conï¬guration Address Register (INT_CFADDR)
Address: 0x0127
7
6
5
4
3
2
1
0
R
INT_CFADDR[7:4]
W
0
0
0
0
Reset
0
0
0
1
0
0
0
0
= Unimplemented or Reserved
Figure 6-5. Interrupt Conï¬guration Address Register (INT_CFADDR)
Read: Anytime
Write: Anytime
Table 6-7. INT_CFADDR Field Descriptions
Field
Description
7â4
Interrupt Request Conï¬guration Data Register Select Bits â These bits determine which of the 128
INT_CFADDR[7:4] conï¬guration data registers are accessible in the 8 register window at INT_CFDATA0â7. The hexadecimal
value written to this register corresponds to the upper nibble of the lower byte of the address of the interrupt
vector, i.e., writing 0xE0 to this register selects the conï¬guration data register block for the 8 interrupt vector
requests starting with vector at address (vector base + 0x00E0) to be accessible as INT_CFDATA0â7.
Note: Writing all 0s selects non-existing conï¬guration registers. In this case write accesses to
INT_CFDATA0â7 will be ignored and read accesses will return all 0.
6.3.2.4 Interrupt Request Conï¬guration Data Registers (INT_CFDATA0â7)
The eight register window visible at addresses INT_CFDATA0â7 contains the conï¬guration data for the
block of eight interrupt requests (out of 128) selected by the interrupt conï¬guration address register
(INT_CFADDR) in ascending order. INT_CFDATA0 represents the interrupt conï¬guration data register
of the vector with the lowest address in this block, while INT_CFDATA7 represents the interrupt
conï¬guration data register of the vector with the highest address, respectively.
MC9S12XE-Family Reference Manual Rev. 1.25
268
Freescale Semiconductor
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