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S912XEP100J5MAG Datasheet, PDF (638/1324 Pages) Freescale Semiconductor, Inc – Features of the MC9S12XE-Family are listed here. Please see Table D-2.for memory options and Table D-2. for the peripheral features that are available on the different family members. | |||
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Chapter 16 Freescaleâs Scalable Controller Area Network (S12MSCANV3)
16.3.3.3 Data Length Register (DLR)
This register keeps the data length ï¬eld of the CAN frame.
Module Base + 0x00XC
7
6
5
4
3
2
1
R
DLC3
DLC2
DLC1
W
Reset:
x
x
x
x
x
x
x
= Unused; always read âxâ
Figure 16-35. Data Length Register (DLR) â Extended Identiï¬er Mapping
0
DLC0
x
Table 16-34. DLR Register Field Descriptions
Field
Description
3-0
DLC[3:0]
Data Length Code Bits â The data length code contains the number of bytes (data byte count) of the respective
message. During the transmission of a remote frame, the data length code is transmitted as programmed while
the number of transmitted data bytes is always 0. The data byte count ranges from 0 to 8 for a data frame.
Table 16-35 shows the effect of setting the DLC bits.
DLC3
0
0
0
0
0
0
0
0
1
Table 16-35. Data Length Codes
Data Length Code
DLC2
0
0
0
0
1
1
1
1
0
DLC1
0
0
1
1
0
0
1
1
0
DLC0
0
1
0
1
0
1
0
1
0
Data Byte
Count
0
1
2
3
4
5
6
7
8
16.3.3.4 Transmit Buffer Priority Register (TBPR)
This register deï¬nes the local priority of the associated message buffer. The local priority is used for the
internal prioritization process of the MSCAN and is deï¬ned to be highest for the smallest binary number.
The MSCAN implements the following internal prioritization mechanisms:
⢠All transmission buffers with a cleared TXEx ï¬ag participate in the prioritization immediately
before the SOF (start of frame) is sent.
MC9S12XE-Family Reference Manual Rev. 1.25
638
Freescale Semiconductor
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