S912XEP100J5MAG Datasheet, PDF (582/1324 Pages) Freescale Semiconductor, Inc – Features of the MC9S12XE-Family are listed here. Please see Table D-2.for memory options and Table D-2. for the peripheral features that are available on the different family members.

Chapter 15 Inter-Integrated Circuit (IICV3) Block Description
This register contains the address the IIC bus will respond to when addressed as a slave; note that it is not
the address sent on the bus during the address transfer.
Table 15-2. IBAD Field Descriptions
Field
Description
7:1
ADR[7:1]
0
Reserved
Slave Address — Bit 1 to bit 7 contain the specific slave address to be used by the IIC bus module.The default
mode of IIC bus is slave mode for an address match on the bus.
Reserved — Bit 0 of the IBAD is reserved for future compatibility. This bit will always read 0.
15.3.1.2 IIC Frequency Divider Register (IBFD)
Module Base + 0x0001
R
W
Reset
7
IBC7
0
6
IBC6
5
IBC5
4
IBC4
3
IBC3
2
IBC2
0
0
0
0
0
= Unimplemented or Reserved
Figure 15-4. IIC Bus Frequency Divider Register (IBFD)
Read and write anytime
1
IBC1
0
0
IBC0
0
Table 15-3. IBFD Field Descriptions
Field
7:0
IBC[7:0]
Description
I Bus Clock Rate 7:0 — This field is used to prescale the clock for bit rate selection. The bit clock generator is
implemented as a prescale divider — IBC7:6, prescaled shift register — IBC5:3 select the prescaler divider and
IBC2-0 select the shift register tap point. The IBC bits are decoded to give the tap and prescale values as shown
in Table 15-4.
Table 15-4. I-Bus Tap and Prescale Values
IBC2-0
(bin)
000
001
010
011
100
101
110
111
SCL Tap
(clocks)
5
6
7
8
9
10
12
15
SDA Tap
(clocks)
1
1
2
2
3
3
4
4
MC9S12XE-Family Reference Manual Rev. 1.25
582
Freescale Semiconductor