S912XEP100J5MAG Datasheet, PDF(672/1324 Page) Freescale Semiconductor, Inc – Features of the MC9S12XE-Family are listed here. Please see Table D-2.for memory options and Table D-2. for the peripheral features that are available on the different family members.

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S912XEP100J5MAG Datasheet, PDF (672/1324 Pages) Freescale Semiconductor, Inc – Features of the MC9S12XE-Family are listed here. Please see Table D-2.for memory options and Table D-2. for the peripheral features that are available on the different family members.

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Chapter 17 Periodic Interrupt Timer (S12PIT24B8CV2)

17.4.1 Timer

As shown in Figure 17-1 and Figure 17-27, the 24-bit timers are built in a two-stage architecture with eight

16-bit modulus down-counters and two 8-bit modulus down-counters. The 16-bit timers are clocked with

two selectable micro time bases which are generated with 8-bit modulus down-counters. Each 16-bit timer

is connected to micro time base 0 or 1 via the PMUX[7:0] bit setting in the PIT Multiplex (PITMUX)

register.

A timer channel is enabled if the module enable bit PITE in the PIT control and force load micro timer

(PITCFLMT) register is set and if the corresponding PCE bit in the PIT channel enable (PITCE) register

is set. Two 8-bit modulus down-counters are used to generate two micro time bases. As soon as a micro

time base is selected for an enabled timer channel, the corresponding micro timer modulus down-counter

will load its start value as speciï¬ed in the PITMTLD0 or PITMTLD1 register and will start down-counting.

Whenever the micro timer down-counter has counted to zero the PITMTLD register is reloaded and the

connected 16-bit modulus down-counters count one cycle.

Whenever a 16-bit timer counter and the connected 8-bit micro timer counter have counted to zero, the

PITLD register is reloaded and the corresponding time-out ï¬ag PTF in the PIT time-out ï¬ag (PITTF)

register is set, as shown in Figure 17-28. The time-out period is a function of the timer load (PITLD) and

micro timer load (PITMTLD) registers and the bus clock fBUS:

time-out period = (PITMTLD + 1) * (PITLD + 1) / fBUS.

For example, for a 40 MHz bus clock, the maximum time-out period equals:

256 * 65536 * 25 ns = 419.43 ms.

The current 16-bit modulus down-counter value can be read via the PITCNT register. The micro timer

down-counter values cannot be read.

The 8-bit micro timers can individually be restarted by writing a one to the corresponding force load micro

timer PFLMT bits in the PIT control and force load micro timer (PITCFLMT) register. The 16-bit timers

can individually be restarted by writing a one to the corresponding force load timer PFLT bits in the PIT

forceload timer (PITFLT) register. If desired, any group of timers and micro timers can be restarted at the

same time by using one 16-bit write to the adjacent PITCFLMT and PITFLT registers with the relevant

bits set, as shown in Figure 17-28.

MC9S12XE-Family Reference Manual Rev. 1.25

672

Freescale Semiconductor

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