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S912XEP100J5MAG Datasheet, PDF (185/1324 Pages) Freescale Semiconductor, Inc – Features of the MC9S12XE-Family are listed here. Please see Table D-2.for memory options and Table D-2. for the peripheral features that are available on the different family members. | |||
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Chapter 2 Port Integration Module (S12XEPIMV1)
2.4.4 Pin interrupts
Ports P, H and J offer pin interrupt capability. The interrupt enable as well as the sensitivity to rising or
falling edges can be individually conï¬gured on per-pin basis. All bits/pins in a port share the same interrupt
vector. Interrupts can be used with the pins conï¬gured as inputs or outputs.
An interrupt is generated when a bit in the port interrupt ï¬ag register and its corresponding port interrupt
enable bit are both set. The pin interrupt feature is also capable to wake up the CPU when it is in STOP or
WAIT mode.
A digital ï¬lter on each pin prevents pulses (Figure 2-109) shorter than a speciï¬ed time from generating an
interrupt. The minimum time varies over process conditions, temperature and voltage (Figure 2-108 and
Table 2-104).
Glitch, ï¬ltered out, no interrupt ï¬ag set
Valid pulse, interrupt ï¬ag set
uncertain
tpign
tpval
Figure 2-108. Interrupt Glitch Filter on Port P, H and J (PPS=0)
Table 2-104. Pulse Detection Criteria
Mode
Pulse
STOP
STOP(1)
Unit
Ignored
tpulse ⤠3 bus clocks
tpulse ⤠tpign
Uncertain
3 < tpulse < 4 bus clocks
tpign < tpulse < tpval
Valid
tpulse ⥠4 bus clocks
tpulse ⥠tpval
1. These values include the spread of the oscillator frequency over temper-
ature, voltage and process.
MC9S12XE-Family Reference Manual Rev. 1.25
Freescale Semiconductor
185
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