S912XEP100J5MAG Datasheet, PDF (139/1324 Pages) Freescale Semiconductor, Inc – Features of the MC9S12XE-Family are listed here. Please see Table D-2.for memory options and Table D-2. for the peripheral features that are available on the different family members.

Chapter 2 Port Integration Module (S12XEPIMV1)
Field
7-0
PTIP
Table 2-42. PTIP Register Field Descriptions
Description
Port P input data—
This register always reads back the buffered state of the associated pins. This can also be used to detect overload
or short circuit conditions on output pins.
2.3.47 Port P Data Direction Register (DDRP)
Address 0x025A
R
W
Reset
7
DDRP7
0
1. Read: Anytime.
Write: Anytime.
6
DDRP6
5
DDRP5
4
DDRP4
3
DDRP3
2
DDRP2
0
0
0
0
0
Figure 2-45. Port P Data Direction Register (DDRP)
Access: User read/write⁽¹⁾
1
0
DDRP1
DDRP0
0
0
Table 2-43. DDRP Register Field Descriptions
Field
7
DDRP
6-0
DDRP
Description
Port P data direction—
This register controls the data direction of pin 7.
The enabled PWM channel 7 forces the I/O state to be an output. If the PWM shutdown feature is enabled this pin
is forced to be an input. In these cases the data direction bit will not change.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
Port P data direction—
The PWM forces the I/O state to be an output for each port line associated with an enabled PWM6-0 channel. In this
case the data direction bit will not change.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
NOTE
Due to internal synchronization circuits, it can take up to 2 bus clock cycles
until the correct value is read on PTP or PTIP registers, when changing the
DDRP register.
MC9S12XE-Family Reference Manual Rev. 1.25
Freescale Semiconductor
139