S912XEP100J5MAG Datasheet, PDF (474/1324 Pages) Freescale Semiconductor, Inc – Features of the MC9S12XE-Family are listed here. Please see Table D-2.for memory options and Table D-2. for the peripheral features that are available on the different family members.

Chapter 11 S12XE Clocks and Reset Generator (S12XECRGV1)
11.3.2.2 S12XECRG Reference Divider Register (REFDV)
The REFDV register provides a finer granularity for the IPLL multiplier steps.
Module Base + 0x0001
7
6
5
4
3
2
1
0
R
REFFRQ[1:0]
W
REFDIV[5:0]
Reset
0
0
0
0
0
0
0
0
Figure 11-4. S12XECRG Reference Divider Register (REFDV)
Read: Anytime
Write: Anytime except when PLLSEL = 1
NOTE
Write to this register initializes the lock detector bit.
f _REF = ₍---_R----_E----_F-^f--^OD-----^SI--_V-^C-----₊-----₁----₎
The REFFRQ[1:0] bit are used to configure the internal PLL filter for optimal stability and lock time. For
correct IPLL operation the REFFRQ[1:0] bits have to be selected according to the actual REFCLK
frequency as shown in Figure 11-3. Setting the REFFRQ[1:0] bits wrong can result in a non functional
IPLL (no locking and/or insufficient stability).
Table 11-3. Reference Clock Frequency Selection
REFCLK Frequency Ranges
1MHz <= f_REF <= 2MHz
2MHz < f_REF <= 6MHz
6MHz < f_REF <= 12MHz
f_REF >12MHz
REFFRQ[1:0]
00
01
10
11
11.3.2.3 S12XECRG Post Divider Register (POSTDIV)
The POSTDIV register controls the frequency ratio between the VCOCLK and PLLCLK. The count in the
final divider divides VCOCLK frequency by 1 or 2*POSTDIV. Note that if POSTDIV = $00 f_PLL= f_VCO
(divide by one).
MC9S12XE-Family Reference Manual Rev. 1.25
474
Freescale Semiconductor