S912XEP100J5MAG Datasheet, PDF (313/1324 Pages) Freescale Semiconductor, Inc – Features of the MC9S12XE-Family are listed here. Please see Table D-2.for memory options and Table D-2. for the peripheral features that are available on the different family members.

Chapter 8 S12X Debug (S12XDBGV3) Module
8.3.2.3 Debug Trace Control Register (DBGTCR)
Address: 0x0022
R
W
Reset
7
6
TSOURCE
0
0
5
4
TRANGE
0
0
3
2
TRCMOD
0
0
Figure 8-5. Debug Trace Control Register (DBGTCR)
Read: Anytime
Write: Bits 7:6 only when S12XDBG is neither secure nor armed.
Bits 5:0 anytime the module is disarmed.
1
0
TALIGN
0
0
Table 8-10. DBGTCR Field Descriptions
Field
Description
7–6
Trace Source Control Bits — The TSOURCE bits select the data source for the tracing session. If the MCU
TSOURCE system is secured, these bits cannot be set and tracing is inhibited. See Table 8-11.
5–4
TRANGE
Trace Range Bits — The TRANGE bits allow filtering of trace information from a selected address range when
tracing from the CPU12X in Detail Mode. The XGATE tracing range cannot be narrowed using these bits. To use
a comparator for range filtering, the corresponding COMPE and SRC bits must remain cleared. If the COMPE
bit is not clear then the comparator will also be used to generate state sequence triggers. If the corresponding
SRC bit is set the comparator is mapped to the XGATE buses, the TRANGE bits have no effect on the valid
address range, memory accesses within the whole memory map are traced. See Table 8-12.
3–2
TRCMOD
Trace Mode Bits — See Section 8.4.5.2 for detailed Trace Mode descriptions. In Normal Mode, change of flow
information is stored. In Loop1 Mode, change of flow information is stored but redundant entries into trace
memory are inhibited. In Detail Mode, address and data for all memory and register accesses is stored. See
Table 8-13.
1–0
Trigger Align Bits — These bits control whether the trigger is aligned to the beginning, end or the middle of a
TALIGN tracing session. See Table 8-14.
Table 8-11. TSOURCE — Trace Source Bit Encoding
TSOURCE
Tracing Source
00
No tracing requested
01
CPU12X
10⁽¹⁾
XGATE
11^1,(2)
Both CPU12X and XGATE
1. No range limitations are allowed. Thus tracing operates as if TRANGE = 00.
2. No Detail Mode tracing supported. If TRCMOD = 10, no information is stored.
MC9S12XE-Family Reference Manual Rev. 1.25
Freescale Semiconductor
313