XQ2V1000 Datasheet, PDF (96/127 Pages) Xilinx, Inc – QPro Virtex-II 1.5V Military QML Platform FPGAs

QPro Virtex-II 1.5V Military QML Platform FPGAs
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BG728 Standard BGA and CG717 Ceramic CGA Packages
As shown in Table 78, the XQ2V3000 QPro Virtex-II device
is available in the BG728 BGA and CG717 CGA packages.
The CG717 has identical pinout as the BG728 (except for
those pins listed as Removed¹) and footprint compatibility. A
summary of the removed pins is shown in Table 77. Follow-
ing this table are the BG728 Standard BGA Package
Specifications (1.27mm pitch) and the CG717 Ceramic
Column Grid Array (CGA) Package Specifications
(1.27mm pitch) The CG717 has 11 fewer GND pins than
the BG728. The BG728 GND pin numbers missing on the
CG717 are shown in Table 77.
Table 77: BG728 GND Pins not available on the CG717¹
BG728 GND Pin Numbers
A2
A27
AG1
AG26
B1
B27
AG2
AG27
A26
AF1
AF27
1. Physical pin does not exist for CG717 package.
Table 78: BG728 BGA and CG717 CGA— XQ2V3000
Bank
Pin Description
Pin
Number
0
IO_L01N_0
B3
0
IO_L01P_0
A3
0
IO_L02N_0
B4
0
IO_L02P_0
A4
0
IO_L03N_0/VRP_0
C5
0
IO_L03P_0/VRN_0
C6
0
IO_L04N_0/VREF_0
B5
0
IO_L04P_0
A5
0
IO_L05N_0
E6
0
IO_L05P_0
D6
0
IO_L06N_0
B6
0
IO_L06P_0
A6
0
IO_L19N_0
E7
0
IO_L19P_0
D8
0
IO_L21N_0
F8
0
IO_L21P_0/VREF_0
E8
0
IO_L22N_0
C7
0
IO_L22P_0
C8
0
IO_L24N_0
B7
0
IO_L24P_0
A7
0
IO_L25N_0
H9
0
IO_L25P_0
J9
0
IO_L27N_0
F9
0
IO_L27P_0/VREF_0
G9
0
IO_L28N_0
E9
Table 78: BG728 BGA and CG717 CGA— XQ2V3000
Bank
Pin Description
Pin
Number
0
IO_L28P_0
D9
0
IO_L30N_0
C9
0
IO_L30P_0
B9
0
IO_L49N_0
A8
0
IO_L49P_0
A9
0
IO_L51N_0
G10
0
IO_L51P_0/VREF_0
H10
0
IO_L52N_0
F10
0
IO_L52P_0
E10
0
IO_L54N_0
D10
0
IO_L54P_0
C10
0
IO_L67N_0
B10
0
IO_L67P_0
A10
0
IO_L69N_0
G11
0
IO_L69P_0/VREF_0
H11
0
IO_L70N_0
F11
0
IO_L70P_0
F12
0
IO_L72N_0
D11
0
IO_L72P_0
C11
0
IO_L73N_0
B11
0
IO_L73P_0
A11
0
IO_L75N_0
H12
0
IO_L75P_0/VREF_0
J12
0
IO_L76N_0
E12
0
IO_L76P_0
D12
96
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