XQ2V1000 Datasheet, PDF (13/127 Pages) Xilinx, Inc – QPro Virtex-II 1.5V Military QML Platform FPGAs

R
Incompatible example:
HSTL_I_DCI input and HSTL_II_DCI input
Table 10 summarizes all standards and voltage supplies.
Table 10: Summary of Voltage Supply Requirements
for All Input and Output Standards
I/O Standard
V_CCO
Output Input
V_REF
Input
Termination Type
Output Input
LVDS_33
N/R ⁽¹⁾
N/R
N/R
LVDSEXT_33
N/R
N/R
N/R
LVPECL_33
SSTL3_I
N/R
N/R
N/R
N/R
1.5
N/R
N/R
SSTL3_II
1.5
N/R
N/R
AGP
1.32
N/R
N/R
LVTTL
N/R
N/R
N/R
LVCMOS33
N/R
N/R
N/R
LVDCI_33
3.3
N/R Series
N/R
LVDCI_DV2_33
N/R Series
N/R
PCI33_3
N/R
N/R
N/R
PCI66_3
3.3 N/R
N/R
N/R
PCIX
N/R
N/R
N/R
LVDS_33_DCI
N/R
N/R
Split
LVDSEXT_33_DCI
N/R
N/R
Split
SSTL3_I_DCI
1.5
N/R
Split
SSTL3_II_DCI
1.5
Split
Split
LVDS_25
N/R
N/R
N/R
LVDSEXT_25
N/R
N/R
N/R
LDT_25
N/R
N/R
N/R
ULVDS_25
N/R N/R
N/R
N/R
BLVDS_25
N/R
N/R
N/R
SSTL2_I
1.25
N/R
N/R
SSTL2_II
2.5
LVCMOS25
1.25
N/R
N/R
N/R
N/R
N/R
LVDCI_25
N/R Series
N/R
LVDCI_DV2_25
N/R Series
N/R
LVDS_25_DCI
2.5 N/R
N/R
Split
LVDSEXT_25_DCI
N/R
N/R
Split
SSTL2_I_DCI
1.25
N/R
Split
SSTL2_II_DCI
1.25
Split
Split
QPro Virtex-II 1.5V Military QML Platform FPGAs
The implementation tools will enforce these design rules.
Table 10: Summary of Voltage Supply Requirements
for All Input and Output Standards (Continued)
I/O Standard
V_CCO
Output Input
V_REF
Input
Termination Type
Output Input
HSTL_III_18
1.1
N/R
N/R
HSTL_IV_18
1.1
N/R
N/R
HSTL_I_18
HSTL_II_18
0.9
N/R
N/R
N/R
0.9
N/R
N/R
SSTL18_I
0.9
N/R
N/R
SSTL18_II
0.9
N/R
N/R
LVCMOS18
N/R
N/R
N/R
LVDCI_18
1.8
N/R Series
N/R
LVDCI_DV2_18
N/R Series
N/R
HSTL_III_DCI_18
1.1
N/R
Single
HSTL_IV_DCI_18
1.8
1.1
Single
Single
HSTL_I_DCI_18
0.9
N/R
Split
HSTL_II_DCI_18
0.9
Split
Split
SSTL18_I_DCI
0.9
N/R
Split
SSTL18_II_DCI
0.9
Split
Split
HSTL_III
0.9
N/R
N/R
HSTL_IV
HSTL_I
0.9
N/R
N/R
N/R
0.75
N/R
N/R
HSTL_II
0.75
N/R
N/R
LVCMOS15
N/R
N/R
N/R
LVDCI_15
1.5
LVDCI_DV2_15
N/R Series
N/R
N/R Series
N/R
GTLP_DCI
HSTL_III_DCI
1
Single Single
1.5
0.9
N/R
Single
HSTL_IV_DCI
0.9
Single
Single
HSTL_I_DCI
0.75
N/R
Split
HSTL_II_DCI
0.75
Split
Split
GTL_DCI
1.2
1.2
0.8
Single
Single
GTLP
GTL
1
N/R
N/R
N/R N/R
0.8
N/R
N/R
Notes:
1. N/R = no requirement.
Digitally Controlled Impedance (DCI)
Today’s chip output signals with fast edge rates require ter-
mination to prevent reflections and maintain signal integrity.
DS122 (v1.1) January 7, 2004
www.xilinx.com
13
Product Specification
1-800-255-7778