XQ2V1000 Datasheet, PDF (58/127 Pages) Xilinx, Inc – QPro Virtex-II 1.5V Military QML Platform FPGAs

QPro Virtex-II 1.5V Military QML Platform FPGAs
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Table 45: IOB Output Switching Characteristics Standard Adjustments (Continued)
Description
Symbol
Standard
Standard-specific adjustments for output delays terminating
at pads (based on standard capacitive load, Csl)
T_{OLVCMOS18_S12}
T_{OLVCMOS18_S16}
T_{OLVCMOS18_F2}
T_{OLVCMOS18_F4}
T_{OLVCMOS18_F6}
T_{OLVCMOS18_F8}
T_{OLVCMOS18_F12}
T_{OLVCMOS18_F16}
T_{OLVCMOS15_S2}
T_{OLVCMOS15_S4}
T_{OLVCMOS15_S6}
T_{OLVCMOS15_S8}
T_{OLVCMOS15_S12}
T_{OLVCMOS15_S16}
T_{OLVCMOS15_F2}
T_{OLVCMOS15_F4}
T_{OLVCMOS15_F6}
T_{OLVCMOS15_F8}
T_{OLVCMOS15_F12}
T_{OLVCMOS15_F16}
T_{OLVDCI_33}
T_{OLVDCI_25}
T_{OLVDCI_18}
T_{OLVDCI_15}
T_{OLVDCI_DV2_33}
T_{OLVDCI_DV2_25}
T_{OLVDCI_DV2_18}
T_{OLVDCI_DV2_15}
T_{OGTL_DCI}
T_{OGTLP_DCI}
T_{OHSTL_I_DCI}
T_{OHSTL_II_DCI}
T_{OHSTL_III_DCI}
T_{OHSTL_IV_DCI}
T_{OHSTL_I_DCI_18}
T_{OHSTL_II_DCI_18}
T_{OHSTL_III_DCI_18}
T_{OHSTL_IV_DCI_18}
12 mA
16 mA
LVCMOS18, Fast, 2 mA
4 mA
6 mA
8 mA
12 mA
16 mA
LVCMOS15, Slow, 2 mA
4 mA
6 mA
8 mA
12 mA
16 mA
LVCMOS15, Fast, 2 mA
4 mA
6 mA
8 mA
12 mA
16 mA
LVDCI_33
LVDCI_25
LVDCI_18
LVDCI_15
LVDCI_DV2_33
LVDCI_DV2_25
LVDCI_DV2_18
LVDCI_DV2_15
GTL_DCI
GTLP_DCI
HSTL_I_DCI
HSTL_II_DCI
HSTL_III_DCI
HSTL_IV_DCI
HSTL_I_DCI_18
HSTL_II_DCI_18
HSTL_III_DCI_18
HSTL_IV_DCI_18
Value
6.28
6.02
6.30
2.15
0.94
0.80
0.30
0.26
21.50
14.48
13.66
11.06
10.25
9.31
5.78
2.27
1.66
1.05
0.84
0.75
0.84
0.88
0.95
2.06
0.13
0.03
0.48
1.36
–0.35
–0.17
0.26
0.07
–0.20
–0.52
0.06
–0.03
–0.16
–0.47
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
58
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DS122 (v1.1) January 7, 2004
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