XQ2V1000 Datasheet, PDF (51/127 Pages) Xilinx, Inc – QPro Virtex-II 1.5V Military QML Platform FPGAs

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QPro Virtex-II 1.5V Military QML Platform FPGAs
LVPECL DC Specifications
These values are valid when driving a 100 Ω differential
load only, i.e., a 100 Ω resistor between the two receiver
pins. The V_OH levels are 200 mV below standard LVPECL
levels and are compatible with devices tolerant of lower
common-mode ranges. Table 40 summarizes the DC output
specifications of LVPECL. For more information on using
LVPECL, see the Virtex-II User Guide.
Table 40: LVPECL DC Specifications
DC Parameter
V_CCO
V_OH
V_OL
V_IH
V_IL
Differential Input Voltage
Min
Max
3.0
1.8
2.11
0.96
1.27
1.49
2.72
0.86 2.125
0.3
–
Min
Max
3.3
1.92
2.28
1.06
1.43
1.49
2.72
0.86 2.125
0.3
–
Min Max
3.6
2.13 2.41
1.30 1.57
1.49 2.72
0.86 2.125
0.3
–
Units
V
V
V
V
V
V
QPro Virtex-II Switching Characteristics
Switching characteristics in this document are specified on
a per-speed-grade basis and can be designated as
Advance, Preliminary, or Production. Each designation is
defined as follows:
Advance: These speed files are based on simulations only
and are typically available soon after device design specifi-
cations are frozen. Although speed grades with this desig-
nation are considered relatively stable and conservative,
some under-reporting might still occur.
Preliminary: These speed files are based on complete ES
(engineering sample) silicon characterization. Devices and
speed grades with this designation are intended to give a
better indication of the expected performance of production
silicon. The probability of under-reporting delays is greatly
reduced as compared to Advance data.
Production: These speed files are released once enough
production silicon of a particular device family member has
been characterized to provide full correlation between
speed files and devices over numerous production lots.
There is no under-reporting of delays, and customers
receive formal notification of any subsequent changes. Typ-
ically, the slowest speed grades transition to Production
before faster speed grades.
Since individual family members are produced at different
times, the migration from one category to another depends
completely on the status of the fabrication process for each
device. Table 41 correlates the current status of each QPro
Virtex-II device with a corresponding speed grade designa-
tion.
Table 41: QPro Virtex-II Device Speed Grade
Designations
Speed Grade Designations
Device
Advance Preliminary Production
XQ2V1000
–4
XQ2V3000
–4
XQ2V6000
–4
All specifications are always representative of worst-case
supply voltage and junction temperature conditions.
Testing of Switching Characteristics
All devices are 100% functionally tested. Internal timing
parameters are derived from measuring internal test pat-
terns. Listed below are representative values. For more
specific, more precise, and worst-case guaranteed data,
use the values reported by the Xilinx static timing analyzer
and back-annotate to the simulation net list. Unless other-
wise noted, values apply to all QPro Virtex-II devices.
DS122 (v1.1) January 7, 2004
www.xilinx.com
51
Product Specification
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