XQ2V1000 Datasheet, PDF (18/127 Pages) Xilinx, Inc – QPro Virtex-II 1.5V Military QML Platform FPGAs

QPro Virtex-II 1.5V Military QML Platform FPGAs
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Configurable Logic Blocks (CLBs)
The Virtex-II configurable logic blocks (CLB) are organized
in an array and are used to build combinatorial and synchro-
nous logic designs. Each CLB element is tied to a switch
matrix to access the general routing matrix, as shown in
Figure 15. A CLB element comprises four similar slices with
fast local feedback within the CLB. The four slices are split
into two columns of two slices with two independent carry
logic chains and one common shift chain.
Switch
Matrix
TBUF X0Y1
TBUF X0Y0
COUT
Slice
X1Y1
COUT
Slice
X1Y0
Slice
X0Y1
SHIFT
CIN
Slice
X0Y0
Fast
Connects
to neighbors
CIN
DS031_32_101600
Figure 15: Virtex-II CLB Element
Slice Description
Each slice includes two 4-input function generators, carry
logic, arithmetic logic gates, wide function multiplexers and
two storage elements. As shown in Figure 16, each 4-input
function generator is programmable as a 4-input LUT, 16
bits of distributed SelectRAM memory, or a 16-bit vari-
able-tap shift register element.
RAM16
ORCY
SRL16
LUT
G
RAM16
MUXFx
CY
Register
SRL16
LUT
F
MUXF5
CY
Register
Arithmetic Logic
DS031_31_100900
Figure 16: Virtex-II Slice Configuration
The output from the function generator in each slice drives
both the slice output and the D input of the storage element.
Figure 17 shows a more detailed view of a single slice.
Configurations
Look-Up Table
Virtex-II function generators are implemented as 4-input
look-up tables (LUTs). Four independent inputs are pro-
vided to each of the two function generators in a slice (F and
G). These function generators are each capable of imple-
menting any arbitrarily defined Boolean function of four
inputs. The propagation delay is therefore independent of
the function implemented. Signals from the function gener-
ators can exit the slice (X or Y output), can input the XOR
dedicated gate (see arithmetic logic), or input the carry-logic
multiplexer (see fast look-ahead carry logic), or feed the D
input of the storage element, or go to the MUXF5 (not
shown in Figure 17).
In addition to the basic LUTs, the Virtex-II slice contains
logic (MUXF5 and MUXFX multiplexers) that combines
function generators to provide any function of five, six,
seven, or eight inputs. The MUXFXs are either MUXF6,
MUXF7, or MUXF8 according to the slice considered in the
CLB. Selected functions up to nine inputs (MUXF5 multi-
plexer) can be implemented in one slice. The MUXFX can
also be a MUXF6, MUXF7, or MUXF8 multiplexer to map
any functions of six, seven, or eight inputs and selected
wide logic functions.
Register/Latch
The storage elements in a Virtex-II slice can be configured
as either edge-triggered D-type flip-flops or level-sensitive
latches. The D input can be directly driven by the X or Y out-
put via the DX or DY input, or by the slice inputs bypassing
the function generators via the BX or BY input. The clock
enable signal (CE) is active High by default. If left uncon-
nected, the clock enable for that storage element defaults to
the active state.
In addition to clock (CK) and clock enable (CE) signals,
each slice has set and reset signals (SR and BY slice
inputs). SR forces the storage element into the state speci-
fied by the attribute SRHIGH or SRLOW. SRHIGH forces a
logic “1” when SR is asserted. SRLOW forces a logic “0”.
When SR is used, a second input (BY) forces the storage
element into the opposite state. The reset condition is pre-
dominant over the set condition. (See Figure 18.)
The initial state after configuration or global initial state is
defined by a separate INIT0 and INIT1 attribute. By default,
setting the SRLOW attribute sets INIT0, and setting the
SRHIGH attribute sets INIT1.
For each slice, set and reset can be set to be synchronous
or asynchronous. Virtex-II devices also have the ability to
set INIT0 and INIT1 independent of SRHIGH and SRLOW.
Control signals CLK, CE, and SR are common to both stor-
age elements in one slice. All control signals have indepen-
dent polarities. Any inverter placed on a control input is
automatically absorbed.
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DS122 (v1.1) January 7, 2004
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