XQ2V1000 Datasheet, PDF (66/127 Pages) Xilinx, Inc – QPro Virtex-II 1.5V Military QML Platform FPGAs

QPro Virtex-II 1.5V Military QML Platform FPGAs
R
Block SelectRAM Switching Characteristics
Table 54: Block SelectRAM Switching Characteristics
Description
Symbol
Min
Min
Sequential Delays
Clock CLK to DOUT output
Setup and Hold Times Before Clock CLK
T_BCKO
-
2.65
ADDR inputs
DIN inputs
EN input
RST input
WEN input
Clock CLK
T_BACK/T_BCKA
0.36/ 0.00
-
T_BDCK/T_BCKD
0.36/ 0.00
-
T_BECK/T_BCKE
1.20/–0.58
-
T_BRCK/T_BCKR
1.65/–0.90
-
T_BWCK/T_BCKW 0.72/–0.25
-
Minimum Pulse Width, High
Minimum Pulse Width, Low
T_BPWH
1.48
-
T_BPWL
1.48
-
TBUF Switching Characteristics
Units
ns
ns
ns
ns
ns
ns
ns
ns
Table 55: TBUF Switching Characteristics
Description
Combinatorial Delays
IN input to OUT output
TRI input to OUT output high-impedance
TRI input to valid data on OUT output
JTAG Test Access Port Switching Characteristics
Symbol
T_IO
T_OFF
T_ON
Min
Max
Units
-
0.58
ns
-
0.55
ns
-
0.55
ns
Table 56: JTAG Test Access Port Switching Characteristics
Description
TMS and TDI Setup times before TCK
TMS and TDI Hold times after TCK
Output delay from clock TCK to output TDO
Maximum TCK clock frequency
Symbol
T_TAPTK
T_TCKTAP
T_TCKTDO
F_TCK
Min Max Units
5.5
-
ns
0.0
-
ns
-
10.0
ns
-
33
MHz
66
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