XQ2V1000 Datasheet, PDF (23/127 Pages) Xilinx, Inc – QPro Virtex-II 1.5V Military QML Platform FPGAs

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QPro Virtex-II 1.5V Military QML Platform FPGAs
Multiplexers
Virtex-II function generators and associated multiplexers
can implement the following:
• 4:1 multiplexer in one slice
• 8:1 multiplexer in two slices
• 16:1 multiplexer in one CLB element (4 slices)
• 32:1 multiplexer in two CLB elements (8 slices)
Each Virtex-II slice has one MUXF5 multiplexer and one
MUXFX multiplexer. The MUXFX multiplexer implements
the MUXF6, MUXF7, or MUXF8, as shown in Figure 24.
Each CLB element has two MUXF6 multiplexers, one
MUXF7 multiplexer and one MUXF8 multiplexer. Examples
of multiplexers are shown in the Virtex-II User Guide
(UG002). Any LUT can implement a 2:1 multiplexer.
Slice S3
G
F
MUXF8 combines
the two MUXF7 outputs
(Two CLBs)
Slice S2
G
F
MUXF6 combines the two MUXF5
outputs from slices S2 and S3
G
Slice S1
F
MUXF7 combines the two MUXF6
outputs from slices S0 and S2
G
Slice S0
F
MUXF6 combines the two MUXF5
outputs from slices S0 and S1
CLB
Figure 24: MUXF5 and MUXFX multiplexers
DS031_08_100201
Fast Lookahead Carry Logic
Dedicated carry logic provides fast arithmetic addition and
subtraction. The Virtex-II CLB has two separate carry
chains, as shown in the Figure 25.
The height of the carry chains is two bits per slice. The carry
chain in the Virtex-II device is running upward. The dedi-
cated carry path and carry multiplexer (MUXCY) can also
be used to cascade function generators for implementing
wide logic functions.
Arithmetic Logic
The arithmetic logic includes an XOR gate that allows a
2-bit full adder to be implemented within a slice. In addition,
a dedicated AND (MULT_AND) gate (shown in Figure 17)
improves the efficiency of multiplier implementation.
DS122 (v1.1) January 7, 2004
www.xilinx.com
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Product Specification
1-800-255-7778