XQ2V1000 Datasheet, PDF (72/127 Pages) Xilinx, Inc – QPro Virtex-II 1.5V Military QML Platform FPGAs

QPro Virtex-II 1.5V Military QML Platform FPGAs
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Miscellaneous Timing Parameters
Table 65: Miscellaneous Timing Parameters
Description
Time Required to Achieve LOCK
Symbol
Constraints
F_CLKIN
Value
Using DLL outputs⁽¹⁾
LOCK_DLL
LOCK_DLL_60
> 60MHz
20.0
LOCK_DLL_50_60
50 - 60 MHz
25.0
LOCK_DLL_40_50
40 - 50 MHz
50.0
LOCK_DLL_30_40
30 - 40 MHz
90.0
LOCK_DLL_24_30
24 - 30 MHz
120.0
Using CLKFX outputs
LOCK_FX_MIN
10.0
LOCK_FX_MAX
10.0
Additional lock time with fine-phase shifting
LOCK_DLL_FINE_SHIFT
50.0
Fine-Phase Shifting
Absolute shifting range
FINE_SHIFT_RANGE
10.0
Delay Lines
Tap delay resolution
DCM_TAP_MIN
30.0
DCM_TAP_MAX
60.0
Notes:
1. “”DLL outputs” is used here to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV.
2. Specification also applies to PSCLK.
Frequency Synthesis
Units
µs
µs
µs
µs
µs
ms
ms
µs
ns
ps
ps
Table 66: Frequency Synthesis
Attribute
CLKFX_MULTIPLY
CLKFX_DIVIDE
Parameter Cross Reference
Table 67: Parameter Cross Reference
Libraries Guide
DLL_CLKOUT_{MIN|MAX}_LF
DFS_CLKOUT_{MIN|MAX}_LF
DLL_CLKIN_{MIN|MAX}_LF
DFS_CLKIN_{MIN|MAX}_LF
DLL_CLKOUT_{MIN|MAX}_HF
DFS_CLKOUT_{MIN|MAX}_HF
DLL_CLKIN_{MIN|MAX}_HF
DFS_CLKIN_{MIN|MAX}_HF
Min
Max
2
32
1
32
Data Sheet
CLKOUT_FREQ_{1X|2X|DV}_LF
CLKOUT_FREQ_FX_LF
CLKIN_FREQ_DLL_LF
CLKIN_FREQ_FX_LF
CLKOUT_FREQ_{1X|DV}_HF
CLKOUT_FREQ_FX_HF
CLKIN_FREQ_DLL_HF
CLKIN_FREQ_FX_HF
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DS122 (v1.1) January 7, 2004
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Product Specification