XQ2V1000 Datasheet, PDF (68/127 Pages) Xilinx, Inc – QPro Virtex-II 1.5V Military QML Platform FPGAs

QPro Virtex-II 1.5V Military QML Platform FPGAs
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QPro Virtex-II Pin-to-Pin Input Parameter Guidelines
All devices are 100% functionally tested. Listed below are representative values for typical pin locations and normal clock
loading. Values are expressed in nanoseconds unless otherwise noted.
Global Clock Setup and Hold for LVTTL Standard, with DCM
Table 59: Global Clock Setup and Hold for LVTTL Standard, with DCM
Description
Symbol
Device
Value Units
Input Setup and Hold Time Relative to Global Clock Input
Signal for LVTTL Standard.
For data input with different standards, adjust the setup time
delay by the values shown in IOB Input Switching
Characteristics Standard Adjustments, page 53.
No Delay
Global Clock and IFF with DCM
T_PSDCM/T_PHDCM
XQ2V1000 1.84/–0.76 ns
XQ2V3000 1.96/–0.76 ns
XQ2V6000 1.96/–0.76 ns
Notes:
1. IFF = Input Flip-Flop or Latch
2. Setup time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is measured
relative to the Global Clock input signal with the slowest route and heaviest load.
Global Clock Setup and Hold for LVTTL Standard, without DCM
Table 60: Global Clock Setup and Hold for LVTTL Standard, without DCM
Description
Symbol
Device
Value Units
Input Setup and Hold Time Relative to Global Clock Input
Signal for LVTTL Standard.⁽¹⁾
For data input with different standards, adjust the setup time
delay by the values shown in IOB Input Switching
Characteristics Standard Adjustments, page 53.
Full Delay
Global Clock and IFF⁽²⁾ without DCM
T_PSFD/T_PHFD
XQ2V1000 2.21/ 0.00 ns
XQ2V3000 2.21/ 0.00 ns
XQ2V6000 2.21/ 0.50 ns
Notes:
1. Setup time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is measured
relative to the Global Clock input signal with the slowest route and heaviest load.
2. IFF = Input Flip-Flop or Latch
3. These values are parametrically measured.
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