XQ2V1000 Datasheet, PDF (71/127 Pages) Xilinx, Inc – QPro Virtex-II 1.5V Military QML Platform FPGAs

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QPro Virtex-II 1.5V Military QML Platform FPGAs
Output Clock Jitter
Table 63: Output Clock Jitter
Description
Symbol
Clock Synthesis Period Jitter
CLK0
CLKOUT_PER_JITT_0
CLK90
CLKOUT_PER_JITT_90
CLK180
CLKOUT_PER_JITT_180
CLK270
CLKOUT_PER_JITT_270
CLK2X, CLK2X180
CLKOUT_PER_JITT_2X
CLKDV (integer division)
CLKOUT_PER_JITT_DV1
CLKDV (non-integer division)
CLKOUT_PER_JITT_DV2
CLKFX, CLKFX180
CLKOUT_PER_JITT_FX
Notes:
1. Values for this parameter are available at http://www.xilinx.com.
Output Clock Phase Alignment
Constraints
Value Units
±100
ps
±150
ps
±150
ps
±150
ps
±200
ps
±150
ps
±300
ps
Note 1 ps
Table 64: Output Clock Phase Alignment
Description
Symbol
Constraints
Value
Phase Offset Between CLKIN and CLKFB
CLKIN/CLKFB
CLKIN_CLKFB_PHASE
±50
Phase Offset Between Any DCM Outputs
All CLK* outputs
CLKOUT_PHASE
±140
Duty Cycle Precision
DLL outputs⁽¹⁾
CLKOUT_DUTY_CYCLE_DLL⁽²⁾
±150
CLKFX outputs
CLKOUT_DUTY_CYCLE_FX
±100
Notes:
1. “”DLL outputs” is used here to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV.
2. CLKOUT_DUTY_CYCLE_DLL applies to the 1X clock outputs (CLK0, CLK90, CLK180, and CLK270) only if
DUTY_CYCLE_CORRECTION = TRUE.
3. Specification also applies to PSCLK.
Units
ps
ps
ps
ps
DS122 (v1.1) January 7, 2004
www.xilinx.com
71
Product Specification
1-800-255-7778