XQ2V1000 Datasheet, PDF (20/127 Pages) Xilinx, Inc – QPro Virtex-II 1.5V Military QML Platform FPGAs

QPro Virtex-II 1.5V Military QML Platform FPGAs
R
FFY
FF
LATCH
DY
D
Q
YQ
CE
Attribute
CK
INIT1
SR REV
INIT0
BY
SRHIGH
SRLOW
FFX
DX
CE
CLK
SR
FF
LATCH
D
Q
CE
CK
SR REV
XQ
Attribute
INIT1
INIT0
SRHIGH
SRLOW
Reset Type
BX
SYNC
ASYNC
DS031_22_110600
Figure 18: Register/Latch Configuration in a Slice
The set and reset functionality of a register or a latch can be
configured as follows:
• No set or reset
• Synchronous set
• Synchronous reset
• Synchronous set and reset
• Asynchronous set (preset)
• Asynchronous reset (clear)
• Asynchronous set and reset (preset and clear)
The synchronous reset has precedence over a set, and an
asynchronous clear has precedence over a preset.
Distributed SelectRAM Memory
Each function generator (LUT) can implement a 16 x 1-bit
synchronous RAM resource called a distributed SelectRAM
element. The SelectRAM elements are configurable within
a CLB to implement the following:
• Single-Port 16 x 8 bit RAM
• Single-Port 32 x 4 bit RAM
• Single-Port 64 x 2 bit RAM
• Single-Port 128 x 1 bit RAM
• Dual-Port 16 x 4 bit RAM
• Dual-Port 32 x 2 bit RAM
• Dual-Port 64 x 1 bit RAM
Distributed SelectRAM memory modules are synchronous
(write) resources. The combinatorial read access time is
extremely fast, while the synchronous write simplifies
high-speed designs. A synchronous read can be imple-
mented with a storage element in the same slice. The dis-
tributed SelectRAM memory and the storage element share
the same clock input. A Write Enable (WE) input is active
High, and is driven by the SR input.
Table 13 shows the number of LUTs (2 per slice) occupied
by each distributed SelectRAM configuration.
Table 13: Distributed SelectRAM Configurations
RAM
Number of LUTs
16 x 1S
1
16 x 1D
2
32 x 1S
2
32 x 1D
4
64 x 1S
4
64 x 1D
8
128 x 1S
8
Notes:
1. S = single-port configuration, and D = dual-port
configuration.
For single-port configurations, distributed SelectRAM mem-
ory has one address port for synchronous writes and asyn-
chronous reads.
For dual-port configurations, distributed SelectRAM mem-
ory has one port for synchronous writes and asynchronous
reads and another port for asynchronous reads. The func-
tion generator (LUT) has separated read address inputs
(A1, A2, A3, A4) and write address inputs (WG1/WF1,
WG2/WF2, WG3/WF3, WG4/WF4).
In single-port mode, read and write addresses share the
same address bus. In dual-port mode, one function genera-
tor (R/W port) is connected with shared read and write
addresses. The second function generator has the A inputs
(read) connected to the second read-only port address and
the W inputs (write) shared with the first read/write port
address.
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DS122 (v1.1) January 7, 2004
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