XQ2V1000 Datasheet, PDF (32/127 Pages) Xilinx, Inc – QPro Virtex-II 1.5V Military QML Platform FPGAs

QPro Virtex-II 1.5V Military QML Platform FPGAs
R
Switch
Matrix
Switch
Matrix
Switch
Matrix
18-Kbit block
SelectRAM
Configuration
The multiplier block is an 18-bit by 18-bit signed multiplier
(2's complement). Both A and B are 18-bit-wide inputs, and
the output is 36 bits. Figure 37 shows a multiplier block.
A[17:0]
Multiplier Block
B[17:0]
MULT 18 x 18
P[35:0]
Switch
Matrix
DS031_40_100400
Figure 37: Multiplier Block
DS031_33_101000
Figure 36: SelectRAM and Multiplier Blocks
Association with Block SelectRAM Memory
The interconnect is designed to allow SelectRAM memory
and multiplier blocks to be used at the same time, but some
interconnect is shared between the SelectRAM and the
multiplier. Thus, SelectRAM memory can be used only up to
18 bits wide when the multiplier is used, because the multi-
plier shares inputs with the upper data bits of the
SelectRAM memory.
This sharing of the interconnect is optimized for an
18-bit-wide block SelectRAM resource feeding the multi-
plier. The use of SelectRAM memory and the multiplier with
an accumulator in LUTs allows for implementation of a digi-
tal signal processor (DSP) multiplier-accumulator (MAC)
function, which is commonly used in finite and infinite
impulse response (FIR and IIR) digital filters.
Locations/Organization
Multiplier organization is identical to the 18 Kbit SelectRAM
organization, because each multiplier is associated with an
18 Kbit block SelectRAM resource.
In addition to the built-in multiplier blocks, the CLB elements
have dedicated logic to implement efficient multipliers in
logic. (Refer to Configurable Logic Blocks (CLBs)).
Table 24: Multiplier Floor Plan
Multipliers
Device
Columns Per Column
Total
XQ2V1000
4
10
40
XQ2V3000
6
16
96
XQ2V6000
6
24
144
32
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DS122 (v1.1) January 7, 2004
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