XQ2V1000 Datasheet, PDF(60/127 Page) Xilinx, Inc – QPro Virtex-II 1.5V Military QML Platform FPGAs

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XQ2V1000 Datasheet, PDF (60/127 Pages) Xilinx, Inc – QPro Virtex-II 1.5V Military QML Platform FPGAs

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QPro Virtex-II 1.5V Military QML Platform FPGAs

I/O Standard Adjustment Measurement Methodology

Input Delay Measurements

Table 46 shows the test setup parameters used for measur-

ing Input standard adjustments (see Table 43, page 53).

Table 46: Input Delay Measurement Methodology

Standard

VL (1)

VH (1)

VMEAS VREF

(3,4) (2,4)

LVTTL

LVCMOS33

LVCMOS25

LVCMOS18

LVCMOS15

PCI33_3

PCI66_3

PCI-X

GTL

GTLP

HSTL Class I

HSTL Class II

HSTL Class III

HSTL Class IV

SSTL3

Class I & II

SSTL2

Class I & II

AGP-2X

LVDS25

3.0

1.4

3.3

1.65

2.5

1.25

1.8

0.9

1.5

0.75

Per PCI Specification

Per PCI-X Specification

VREF â 0.2

VREF â 0.5

VREF + 0.2

VREF + 0.5

VREF

VREF â 1.00 VREF + 1.00 VREF

VREF â 0.75 VREF + 0.75 VREF

VREF â

(0.2 xVCCO)

1.2 â 0.125

VREF +

(0.2 x VCCO)

1.2 + 0.125

VREF

1.2

0.80

1.0

0.75

0.90

1.5

1.25

Per

AGP

Spec

Output Delay Measurements

Output delays are measured using a Tektronix P6245

TDS500/600 probe (< 1 pf) across approximately 4" of FR4

microstrip trace. Standard termination was used for all test-

ing. (See Virtex-II Platform FPGA User Guide for details.)

The propagation delay of the 4" trace is characterized sep-

arately and subtracted from the final measurement, and is

therefore not included in the generalized test setup shown in

Figure 51.

Measurements and test conditions are reflected in the IBIS

models except where the IBIS format precludes it. (IBIS

models can be found on the web at http://support.xil-

inx.com/support/sw_ibis.htm.) Parameters VREF, RREF,

CREF, and VMEAS fully describe the test conditions for each

I/O standard. The most accurate prediction of propagation

delay in any given application can be obtained through IBIS

simulation, using the following method:

1. Simulate the output driver of choice into the generalized

test setup, using values from Table 47.

2. Record the time to VMEAS.

3. Simulate the output driver of choice into the actual PCB

trace and load, using the appropriate IBIS model or

capacitance value to represent the load.

4. Record the time to VMEAS.

5. Compare the results of steps 2 and 4. The increase or

decrease in delay should be added to or subtracted

from the I/O Output Standard Adjustment value

(Table 45) to yield the actual worst-case propagation

delay (clock-to-input) of the PCB trace.

VREF

FPGA Output

RREF

LVDS33

1.2 â 0.125 1.2 + 0.125 1.2

LVDSEXT25

LVDSEXT33

ULVDS25

LDT25

1.2 â 0.125 1.2 + 0.125 1.2

0.6 â 0.125 0.6 + 0.125 0.6

VMEAS

(voltage level at which

delay measurement is taken)

CREF

(probe capacitance)

LVPECL

1.6 â 0.3

1.6 + 0.3

1.6

Notes:

1. Input waveform switches between VLand VH.

2. Measurements are made at typical, minimum, and maximum VREF

values. Reported delays reflect worst case of these measurements.

VREF values listed are typical. See Virtex-II Platform FPGA User

Guide for min/max specifications.

3. Input voltage level from which measurement starts.

4. Note that this is an input voltage reference that bears no relation to

the VREF / VMEAS parameters found in IBIS models and/or noted in

Figure 51.

ds083-3_06a_092503

Figure 51: Generalized Test Setup

www.xilinx.com

DS122 (v1.1) January 7, 2004

1-800-255-7778

Product Specification

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