XQ2V1000 Datasheet, PDF (36/127 Pages) Xilinx, Inc – QPro Virtex-II 1.5V Military QML Platform FPGAs

QPro Virtex-II 1.5V Military QML Platform FPGAs
R
Digital Clock Manager (DCM)
The Virtex-II DCM offers a wide range of powerful clock
management features:
• Clock De-skew: The DCM generates new system
clocks (either internally or externally to the FPGA),
which are phase-aligned to the input clock, thus
eliminating clock distribution delays.
• Frequency Synthesis: The DCM generates a wide
range of output clock frequencies, performing very
flexible clock multiplication and division.
• Phase Shifting: The DCM provides both coarse phase
shifting and fine-grained phase shifting with dynamic
phase shift control.
The DCM utilizes fully digital delay lines allowing robust
high-precision control of clock phase and frequency. It also
utilizes fully digital feedback systems, operating dynamically
to compensate for temperature and voltage variations dur-
ing operation.
Up to four of the nine DCM clock outputs can drive inputs to
global clock buffers or global clock multiplexer buffers simul-
taneously (see Figure 46). All DCM clock outputs can simul-
taneously drive general routing resources, including routes
to output buffers.
DCM
CLKIN
CLKFB
RST
DSSEN
CLK0
CLK90
CLK180
CLK270
CLK2X
CLK2X180
CLKDV
PSINCDEC _CLKFX
PSEN
CLKFX180
PSCLK
LOCKED
STATUS[7:0]
clock signal
PSDONE
control signal
DS031_67_110403
Figure 46: Digital Clock Manager
The DCM can be configured to delay the completion of the
Virtex-II configuration process until after the DCM has
achieved lock. This guarantees that the chip does not begin
operating until after the system clocks generated by the
DCM have stabilized.
The DCM has the following general control signals:
• RST input pin: resets the entire DCM.
• LOCKED output pin: asserted High when all enabled
DCM circuits have locked.
• STATUS output pins (active High): shown in Table 25.
Table 25: DCM Status Pins
Status Pin
0
1
2
3
4
5
6
7
Function
Phase Shift Overflow
CLKIN Stopped
CLKFX Stopped
N/A
N/A
N/A
N/A
N/A
Clock De-Skew
The DCM de-skews the output clocks relative to the input
clock by automatically adjusting a digital delay line. Addi-
tional delay is introduced so that clock edges arrive at inter-
nal registers and block RAMs simultaneously with the clock
edges arriving at the input clock pad. Alternatively, external
clocks, which are also de-skewed relative to the input clock,
can be generated for board-level routing. All DCM output
clocks are phase-aligned to CLK0 and, therefore, are also
phase-aligned to the input clock.
To achieve clock de-skew, the CLKFB input must be con-
nected, and its source must be either CLK0 or CLK2X.
CLKFB must always be connected, unless only the CLKFX
or CLKFX180 outputs are used and de-skew is not required.
Frequency Synthesis
The DCM provides flexible methods for generating new
clock frequencies. Each method has a different operating
frequency range and different AC characteristics. The
CLK2X and CLK2X180 outputs double the clock frequency.
The CLKDV output creates divided output clocks with divi-
sion options of 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 5.5, 6, 6.5, 7, 7.5,
8, 9, 10, 11, 12, 13, 14, 15, and 16.
The CLKFX and CLKFX180 outputs can be used to pro-
duce clocks at the following frequency:
FREQ_CLKFX = (M/D) * FREQ_CLKIN
where M and D are two integers. Specifications for M and D
are provided under DCM Timing Parameters. By default,
M=4 and D=1, which results in a clock output frequency four
times faster than the clock input frequency (CLKIN).
CLK2X180 is phase shifted 180 degrees relative to CLK2X.
CLKFX180 is phase shifted 180 degrees relative to CLKFX.
All frequency synthesis outputs automatically have 50/50
duty cycles (with the exception of the CLKDV output when
performing a non-integer divide in high-frequency mode).
Note that CLK2X and CLK2X180 are not available in
high-frequency mode.
36
www.xilinx.com
DS122 (v1.1) January 7, 2004
1-800-255-7778
Product Specification