XQ2V1000 Datasheet, PDF (44/127 Pages) Xilinx, Inc – QPro Virtex-II 1.5V Military QML Platform FPGAs

QPro Virtex-II 1.5V Military QML Platform FPGAs
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Table 29: Virtex-II Configuration Mode Pin Settings
Configuration Mode⁽¹⁾
M2 M1
M0
Master Serial
0
0
0
CCLK Direction
Out
Data Width
1
Serial D_OUT(2)
Yes
Slave Serial
1
1
1
In
1
Yes
Master SelectMAP
0
1
1
Out
8
No
Slave SelectMAP
1
1
0
In
8
No
Boundary Scan
1
0
1
N/A
1
No
Notes:
1. The HSWAP_EN pin controls the pullups. Setting M2, M1, and M0 selects the configuration mode, while the HSWAP_EN pin
controls whether or not the pullups are used.
2. Daisy chaining is possible only in modes where Serial D_OUT is used. For example, in SelectMAP modes, the first device does NOT
support daisy chaining of downstream devices.
Table 30 lists the total number of bits required to configure
each device.
Table 30: Virtex-II Bitstream Lengths
Device
# of Configuration Bits
XQ2V1000
3,753,432
XQ2V3000
9,595,304
XQ2V6000
19,760,560
Notes:
1. These values are only valid for STEPPING LEVEL 1.
2. Only STEPPING LEVEL 1 should be used with QPro
devices.
Configuration Sequence
The configuration of Virtex-II devices is a three-phase pro-
cess after Power On Reset or POR. POR occurs when
V_CCINT is greater than 1.2V, V_CCAUX is greater than 2.5V,
and V_CCO (bank 4) is greater than 1.5V. Once the POR volt-
ages have been reached, the three-phase process begins.
First, the configuration memory is cleared. Next, con-
figuration data is loaded into the memory, and finally, the
logic is activated by a start-up process.
Configuration is automatically initiated on power-up unless
it is delayed by the user. The INIT_B pin can be held Low
using an open-drain driver. An open-drain is required since
INIT_B is a bidirectional open-drain pin that is held Low by a
Virtex-II FPGA device while the configuration memory is
being cleared. Extending the time that the pin is Low causes
the configuration sequencer to wait. Thus, configuration is
delayed by preventing entry into the phase where data is
loaded.
The configuration process can also be initiated by asserting
the PROG_B pin. The end of the memory-clearing phase is
signaled by the INIT_B pin going High, and the completion
of the entire process is signaled by the DONE pin going
High. The Global Set/Reset (GSR) signal is pulsed after the
last frame of configuration data is written but before the
start-up sequence. The GSR signal resets all flip-flops on
the device.
The default start-up sequence is that one CCLK cycle after
DONE goes High, the global 3-state signal (GTS) is
released. This permits device outputs to turn on as neces-
sary. One CCLK cycle later, the Global Write Enable (GWE)
signal is released. This permits the internal storage ele-
ments to begin changing state in response to the logic and
the user clock.
The relative timing of these events can be changed via con-
figuration options in software. In addition, the GTS and
GWE events can be made dependent on the DONE pins of
multiple devices all going High, forcing the devices to start
synchronously. The sequence can also be paused at any
stage, until lock has been achieved on any or all DCMs, as
well as the DCI.
Readback
In this mode, configuration data from the Virtex-II FPGA
device can be read back. Readback is supported only in the
SelectMAP (master and slave) and Boundary Scan modes.
Along with the configuration data, it is possible to read back
the contents of all registers, distributed SelectRAM, and
block RAM resources. This capability is used for real-time
debugging. For more detailed configuration information, see
the Virtex-II User Guide (UG002).
Bitstream Encryption
Virtex-II devices have an on-chip decryptor using one or two
sets of three keys for triple-key Data Encryption Standard
(DES) operation. Xilinx software tools offer an optional
encryption of the configuration data (bitstream) with a tri-
ple-key DES determined by the designer.
The keys are stored in the FPGA by JTAG instruction and
retained by a battery connected to the V_BATT pin, when the
device is not powered. Virtex-II devices can be configured
with the corresponding encrypted bitstream, using any of
the configuration modes described previously.
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