XQ2V1000 Datasheet, PDF (57/127 Pages) Xilinx, Inc – QPro Virtex-II 1.5V Military QML Platform FPGAs

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QPro Virtex-II 1.5V Military QML Platform FPGAs
Table 45: IOB Output Switching Characteristics Standard Adjustments (Continued)
Description
Symbol
Standard
Standard-specific adjustments for output delays terminating
at pads (based on standard capacitive load, Csl)
T_{OHSTL_IV_18}
T_{OSSTL2_I}
T_{OSSTL2_II}
T_{OSSTL3_I}
T_{OSSTL3_II}
T_OAGP
T_{OLVCMOS33_S2}
T_{OLVCMOS33_S4}
T_{OLVCMOS33_S6}
T_{OLVCMOS33_S8}
T_{OLVCMOS33_S12}
T_{OLVCMOS33_S16}
T_{OLVCMOS33_S24}
T_{OLVCMOS33_F2}
T_{OLVCMOS33_F4}
T_{OLVCMOS33_F6}
T_{OLVCMOS33_F8}
T_{OLVCMOS33_F12}
T_{OLVCMOS33_F16}
T_{OLVCMOS33_F24}
T_{OLVCMOS25_S2}
T_{OLVCMOS25_S4}
T_{OLVCMOS25_S6}
T_{OLVCMOS25_S8}
T_{OLVCMOS25_S12}
T_{OLVCMOS25_S16}
T_{OLVCMOS25_S24}
T_{OLVCMOS25_F2}
T_{OLVCMOS25_F4}
T_{OLVCMOS25_F6}
T_{OLVCMOS25_F8}
T_{OLVCMOS25_F12}
T_{OLVCMOS25_F16}
T_{OLVCMOS25_F24}
T_{OLVCMOS18_S2}
T_{OLVCMOS18_S4}
T_{OLVCMOS18_S6}
T_{OLVCMOS18_S8}
HSTL IV_18
SSTL2 I
SSTL2 II
SSTL3 I
SSTL3 II
AGP
LVCMOS33, Slow, 2 mA
4 mA
6 mA
8 mA
12 mA
16 mA
24 mA
LVCMOS33, Fast, 2 mA
4 mA
6 mA
8 mA
12 mA
16 mA
24 mA
LVCMOS25, Slow, 2 mA
4 mA
6 mA
8 mA
12 mA
16 mA
24 mA
LVCMOS25, Fast, 2 mA
4 mA
6 mA
8 mA
12 mA
16 mA
24 mA
LVCMOS18, Slow, 2 mA
4 mA
6 mA
8 mA
Value
–0.44
0.24
–0.18
0.33
–0.05
–0.31
8.70
4.95
3.78
2.60
2.16
1.40
1.34
6.60
2.81
1.45
0.54
0.31
–0.15
–0.23
10.33
5.67
5.13
4.38
3.22
2.67
2.27
4.60
1.30
0.81
0.37
0.03
–0.21
–0.40
17.71
11.57
8.53
7.78
Units
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DS122 (v1.1) January 7, 2004
www.xilinx.com
57
Product Specification
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