XQ2V1000 Datasheet, PDF (70/127 Pages) Xilinx, Inc – QPro Virtex-II 1.5V Military QML Platform FPGAs

QPro Virtex-II 1.5V Military QML Platform FPGAs
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Input Clock Tolerances
Table 62: Input Clock Tolerances
Description
Input Clock Low/High Pulse Width
Symbol
Constraints
F_CLKIN
Min
Max Units
PSCLK
PSCLK_PULSE
< 1MHz
25.00
ns
1 – 10 MHz
25.00
ns
10 – 25 MHz
10.00
ns
25 – 50 MHz
5.00
ns
50 – 100 MHz
3.00
ns
PSCLK and CLKIN⁽²⁾
100 – 150 MHz
2.40
ns
PSCLK_PULSE and
CLKIN_PULSE
150 – 200 MHz
2.00
ns
200 – 250 MHz
1.80
ns
250 – 300 MHz
1.50
ns
300 – 350 MHz
1.30
ns
350 – 400 MHz
1.15
ns
> 400 MHz
1.05
ns
Input Clock Cycle-Cycle Jitter (Low Frequency Mode)
CLKIN (using DLL outputs)⁽¹⁾
CLKIN_CYC_JITT_DLL_LF
CLKIN (using CLKFX outputs)⁽²⁾
CLKIN_CYC_JITT_FX_LF
±300 ps
±300 ps
Input Clock Cycle-Cycle Jitter (High Frequency Mode)
CLKIN (using DLL outputs)⁽¹⁾
CLKIN_CYC_JITT_DLL_HF
CLKIN (using CLKFX outputs)⁽²⁾
CLKIN_CYC_JITT_FX_HF
±150 ps
±150 ps
Input Clock Period Jitter (Low Frequency Mode)
CLKIN (using DLL outputs)⁽¹⁾
CLKIN (using CLKFX outputs)⁽²⁾
CLKIN_PER_JITT_DLL_LF
CLKIN_PER_JITT_FX_LF
±1
ns
±1
ns
Input Clock Period Jitter (High Frequency Mode)
CLKIN (using DLL outputs)⁽¹⁾
CLKIN (using CLKFX outputs)⁽²⁾
CLKIN_PER_JITT_DLL_HF
CLKIN_PER_JITT_FX_HF
±1
ns
±1
ns
Feedback Clock Path Delay Variation
CLKFB off-chip feedback
CLKFB_DELAY_VAR_EXT
±1
ns
Notes:
1. “”DLL outputs” is used here to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV.
2. If both DLL and CLKFX outputs are used, follow the more restrictive specification.
3. If the DCM phase shift feature is used and the CLKIN frequency > 200 MHz, the CLKIN duty cycle must be within ±5% (45/55 to
55/45).
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DS122 (v1.1) January 7, 2004
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