XQ2V1000 Datasheet, PDF (63/127 Pages) Xilinx, Inc – QPro Virtex-II 1.5V Military QML Platform FPGAs

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QPro Virtex-II 1.5V Military QML Platform FPGAs
CLB Distributed RAM Switching Characteristics
Table 50: CLB Distributed RAM Switching Characteristics
Description
Sequential Delays
Clock CLK to X/Y outputs (WE active) in 16 x 1 mode
Clock CLK to X/Y outputs (WE active) in 32 x 1 mode
Clock CLK to F5 output
Setup and Hold Times Before/After Clock CLK
BX/BY data inputs (DIN)
F/G address inputs
SR input (WS)
Clock CLK
Minimum Pulse Width, High
Minimum Pulse Width, Low
Minimum clock period to meet address write cycle time
CLB Shift Register Switching Characteristics
Symbol
Min
Max
T_SHCKO16
-
T_SHCKO32
-
T_SHCKOF5
-
T_DS/T_DH
T_AS/T_AH
T_WES/T_WEH
0.67/–0.11
0.50/ 0.00
0.53/–0.01
T_WPH
T_WPL
T_WC
0.72
0.72
1.44
2.05
2.49
2.23
-
-
-
-
-
-
Table 51: CLB Shift Register Switching Characteristics
Description
Sequential Delays
Clock CLK to X/Y outputs
Clock CLK to X/Y outputs
Clock CLK to XB output via MC15 LUT output
Clock CLK to YB output via MC15 LUT output
Clock CLK to Shiftout
Clock CLK to F5 output
Setup and Hold Times Before/After Clock CLK
BX/BY data inputs (DIN)
SR input (WS)
Clock CLK
Minimum Pulse Width, High
Minimum Pulse Width, Low
Symbol
Min
Max
T_REG
-
T_REG32
-
T_REGXB
-
T_REGYB
-
T_CKSH
-
T_REGF5
-
T_SRLDS/T_SRLDH
T_WSS/T_WSH
0.67/–0.09
0.24/–0.08
T_SRPH
T_SRPL
0.72
0.72
2.92
3.35
2.82
2.75
2.43
3.09
-
-
-
-
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DS122 (v1.1) January 7, 2004
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Product Specification
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