XQ2V1000 Datasheet, PDF (40/127 Pages) Xilinx, Inc – QPro Virtex-II 1.5V Military QML Platform FPGAs

QPro Virtex-II 1.5V Military QML Platform FPGAs
R
Place-and-route software takes advantage of this regular
array to deliver optimum system performance and fast com-
pile times. The segmented routing resources are essential
to guarantee IP cores portability and to efficiently handle an
Hierarchical Routing Resources
Most Virtex-II signals are routed using the global routing
resources, which are located in horizontal and vertical rout-
ing channels between each switch matrix.
As shown in Figure 50, Virtex-II devices have fully buffered
programmable interconnections, with a number of
incremental design flow that is based on modular imple-
mentations. Total design time is reduced due to fewer and
shorter design iterations.
resources counted between any two adjacent switch matrix
rows or columns. Fanout has minimal impact on the perfor-
mance of each net.
24 Horizontal Long Lines
24 Vertical Long Lines
120 Horizontal Hex Lines
120 Vertical Hex Lines
40 Horizontal Double Lines
40 Vertical Double Lines
16 Direct Connections
(total in all four directions)
8 Fast Connects
Figure 50: Hierarchical Routing Resources
DS031_60_110403
In Figure 50:
• Long lines are bidirectional wires that distribute signals
across the device. Vertical and horizontal long lines
span the full height and width of the device.
• Hex lines route signals to every third or sixth block
away in all four directions. Organized in a staggered
pattern, hex lines can only be driven from one end.
Hex-line signals can be accessed either at the
endpoints or at the midpoint (three blocks from the
source).
• Double lines route signals to every first or second block
away in all four directions. Organized in a staggered
pattern, double lines can be driven only at their
endpoints. Double-line signals can be accessed either
at the endpoints or at the midpoint (one block from the
source).
• Direct connect lines route signals to neighboring
blocks: vertically, horizontally, and diagonally.
• Fast connect lines are the internal CLB local
interconnections from LUT outputs to LUT inputs.
Dedicated Routing
In addition to the global and local routing resources, dedi-
cated signals are available:
• There are eight global clock nets per quadrant (see
Global Clock Multiplexer Buffers).
• Horizontal routing resources are provided for on-chip
3-state buses. Four partitionable bus lines are provided
per CLB row, permitting multiple buses within a row.
(See 3-State Buffers.)
• Two dedicated carry-chain resources per slice column
(two per CLB column) propagate carry-chain MUXCY
40
www.xilinx.com
DS122 (v1.1) January 7, 2004
1-800-255-7778
Product Specification