XQ2V1000 Datasheet, PDF (56/127 Pages) Xilinx, Inc – QPro Virtex-II 1.5V Military QML Platform FPGAs

QPro Virtex-II 1.5V Military QML Platform FPGAs
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IOB Output Switching Characteristics Standard Adjustments
Output delays terminating at a pad are specified for LVTTL with 12 mA drive and fast slew rate. For other standards, adjust
the delays by the values shown.
Table 45: IOB Output Switching Characteristics Standard Adjustments
Description
Symbol
Output Delay Adjustments
Standard-specific adjustments for output delays terminating
at pads (based on standard capacitive load, Csl)
T_{OLVTTL_S2}
T_{OLVTTL_S4}
T_{OLVTTL_S6}
T_{OLVTTL_S8}
T_{OLVTTL_S12}
T_{OLVTTL_S16}
T_{OLVTTL_S24}
T_{OLVTTL_F2}
T_{OLVTTL_F4}
T_{OLVTTL_F6}
T_{OLVTTL_F8}
T_{OLVTTL_F12}
T_{OLVTTL_F16}
T_{OLVTTL_F24}
T_{OLVDS_25}
T_{OLVDS_33}
T_{OLVDSEXT_25}
T_{OLVDSEXT_33}
T_{OLDT_25}
T_{OBLVDS_25}
T_{OULVDS_25}
T_{OLVPECL_33}
T_{OPCI33_3}
T_{OPCI66_3}
T_OPCIX
T_OGTL
T_OGTLP
T_{OHSTL_I}
T_{OHSTL_II}
T_{OHSTL_III}
T_{OHSTL_IV}
T_{OHSTL_I_18}
T_{OHSTL_II_18}
T_{OHSTL_III_18}
Standard
Value Units
LVTTL, Slow, 2 mA
10.68 ns
4 mA
6.55
ns
6 mA
4.66
ns
8 mA
3.26
ns
12 mA
2.63
ns
16 mA
1.93
ns
24 mA
1.43
ns
LVTTL, Fast, 2 mA
7.39
ns
4 mA
3.17
ns
6 mA
1.78
ns
8 mA
0.52
ns
12 mA
0.00
ns
16 mA
–0.15 ns
24 mA
–0.26 ns
LVDS
–0.36 ns
LVDS
–0.29 ns
LVDS
–0.21 ns
LVDS
–0.19 ns
LDT
–0.23 ns
BLVDS
0.76
ns
ULVDS
–0.23 ns
LVPECL
0.33
ns
PCI, 33 MHz, 3.3 V
1.31
ns
PCI, 66 MHz, 3.3 V
–0.01 ns
PCI–X, 133 MHz, 3.3 V –0.01 ns
GTL
–0.36 ns
GTLP
–0.20 ns
HSTL I
0.29
ns
HSTL II
–0.17 ns
HSTL III
–0.19 ns
HSTL IV
–0.45 ns
HSTL I_18
–0.04 ns
HSTL II_18
–0.20 ns
HSTL III_18
–0.18 ns
56
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DS122 (v1.1) January 7, 2004
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