XQ2V1000 Datasheet, PDF (30/127 Pages) Xilinx, Inc – QPro Virtex-II 1.5V Military QML Platform FPGAs

QPro Virtex-II 1.5V Military QML Platform FPGAs
R
Data_in
Internal
DI _Memory
DO
No change during write
CLK
WE
Data_in
New
Address
aa
RAM Contents
Old
New
Data_out
Last Read Cycle Content (no change)
Figure 34: NO_CHANGE Mode
DS031_12_102000
Control Pins and Attributes
Virtex-II SelectRAM memory has two independent ports
with the control signals described in Table 21. All control
inputs including the clock have an optional inversion.
Table 21: Control Functions
Control Signal
Function
CLK
Read and Write Clock
EN
Enable affects Read, Write, Set, Reset
WE
Write Enable
SSR
Set DO register to SRVAL (attribute)
Initial memory content is determined by the INIT_xx
attributes. Separate attributes determine the output register
value after device configuration (INIT) and SSR is asserted
(SRVAL). Both attributes (INIT_B and SRVAL) are available
for each port when a block SelectRAM resource is config-
ured as dual-port RAM.
Locations
Virtex-II SelectRAM memory blocks are located in either
four or six columns. The number of blocks per column
depends of the device array size and is equivalent to the
number of CLBs in a column divided by four. Column loca-
tions are shown in Table 22.
Table 22: SelectRAM Memory Floor Plan
SelectRAM Blocks
Device
Columns Per Column
Total
XQ2V1000
4
10
40
XQ2V3000
6
16
96
XQ2V6000
6
24
144
30
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DS122 (v1.1) January 7, 2004
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Product Specification